2022-09-12 20:46:03 +00:00
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// Copyright © 2022, Microsoft Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use anyhow::anyhow;
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#[cfg(target_arch = "aarch64")]
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use arch::aarch64::layout::{TPM_SIZE, TPM_START};
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#[cfg(target_arch = "x86_64")]
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use arch::x86_64::layout::{TPM_SIZE, TPM_START};
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use phf::phf_map;
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use std::cmp;
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use std::sync::{Arc, Barrier};
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use thiserror::Error;
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use tpm::emulator::{BackendCmd, Emulator};
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use tpm::TPM_CRB_BUFFER_MAX;
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use tpm::TPM_SUCCESS;
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use vm_device::BusDevice;
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#[derive(Error, Debug)]
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pub enum Error {
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#[error("Emulator doesn't implement min required capabilities: {0}")]
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CheckCaps(#[source] anyhow::Error),
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#[error("Failed to initialize tpm: {0}")]
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Init(#[source] anyhow::Error),
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#[error("Failed to deliver tpm Command: {0}")]
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DeliverRequest(#[source] anyhow::Error),
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}
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type Result<T> = anyhow::Result<T, Error>;
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/* crb 32-bit registers */
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const CRB_LOC_STATE: u32 = 0x0;
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//Register Fields
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// Field => (start, length)
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// start: lowest bit in the bit field numbered from 0
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// length: length of the bit field
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const CRB_LOC_STATE_FIELDS: phf::Map<&str, [u32; 2]> = phf_map! {
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"tpmEstablished" => [0, 1],
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"locAssigned" => [1,1],
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"activeLocality"=> [2, 3],
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"reserved" => [5, 2],
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"tpmRegValidSts" => [7, 1]
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};
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const CRB_LOC_CTRL: u32 = 0x08;
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const CRB_LOC_CTRL_REQUEST_ACCESS: u32 = 1 << 0;
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const CRB_LOC_CTRL_RELINQUISH: u32 = 1 << 1;
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const CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: u32 = 1 << 3;
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const CRB_LOC_STS: u32 = 0x0C;
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const CRB_LOC_STS_FIELDS: phf::Map<&str, [u32; 2]> = phf_map! {
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"Granted" => [0, 1],
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"beenSeized" => [1,1]
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};
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const CRB_INTF_ID: u32 = 0x30;
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const CRB_INTF_ID_FIELDS: phf::Map<&str, [u32; 2]> = phf_map! {
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"InterfaceType" => [0, 4],
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"InterfaceVersion" => [4, 4],
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"CapLocality" => [8, 1],
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"CapCRBIdleBypass" => [9, 1],
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"Reserved1" => [10, 1],
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"CapDataXferSizeSupport" => [11, 2],
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"CapFIFO" => [13, 1],
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"CapCRB" => [14, 1],
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"CapIFRes" => [15, 2],
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"InterfaceSelector" => [17, 2],
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"IntfSelLock" => [19, 1],
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"Reserved2" => [20, 4],
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"RID" => [24, 8]
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};
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const CRB_INTF_ID2: u32 = 0x34;
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const CRB_INTF_ID2_FIELDS: phf::Map<&str, [u32; 2]> = phf_map! {
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"VID" => [0, 16],
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"DID" => [16, 16]
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};
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const CRB_CTRL_REQ: u32 = 0x40;
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const CRB_CTRL_REQ_CMD_READY: u32 = 1 << 0;
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const CRB_CTRL_REQ_GO_IDLE: u32 = 1 << 1;
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const CRB_CTRL_STS: u32 = 0x44;
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const CRB_CTRL_STS_FIELDS: phf::Map<&str, [u32; 2]> = phf_map! {
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"tpmSts" => [0, 1],
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"tpmIdle" => [1, 1]
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};
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const CRB_CTRL_CANCEL: u32 = 0x48;
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const CRB_CANCEL_INVOKE: u32 = 1 << 0;
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const CRB_CTRL_START: u32 = 0x4C;
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const CRB_START_INVOKE: u32 = 1 << 0;
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const CRB_CTRL_CMD_LADDR: u32 = 0x5C;
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const CRB_CTRL_CMD_HADDR: u32 = 0x60;
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const CRB_CTRL_RSP_SIZE: u32 = 0x64;
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const CRB_CTRL_RSP_ADDR: u32 = 0x68;
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const CRB_DATA_BUFFER: u32 = 0x80;
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const TPM_CRB_NO_LOCALITY: u32 = 0xff;
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const TPM_CRB_ADDR_BASE: u32 = TPM_START.0 as u32;
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const TPM_CRB_ADDR_SIZE: usize = TPM_SIZE as usize;
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2023-01-24 23:45:10 +00:00
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const TPM_CRB_R_MAX: usize = CRB_DATA_BUFFER as usize;
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2022-09-12 20:46:03 +00:00
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// CRB Protocol details
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const CRB_INTF_TYPE_CRB_ACTIVE: u32 = 0b1;
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const CRB_INTF_VERSION_CRB: u32 = 0b1;
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const CRB_INTF_CAP_LOCALITY_0_ONLY: u32 = 0b0;
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const CRB_INTF_CAP_IDLE_FAST: u32 = 0b0;
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const CRB_INTF_CAP_XFER_SIZE_64: u32 = 0b11;
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const CRB_INTF_CAP_FIFO_NOT_SUPPORTED: u32 = 0b0;
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const CRB_INTF_CAP_CRB_SUPPORTED: u32 = 0b1;
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const CRB_INTF_IF_SELECTOR_CRB: u32 = 0b1;
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const PCI_VENDOR_ID_IBM: u32 = 0x1014;
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const CRB_CTRL_CMD_SIZE_REG: u32 = 0x58;
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const CRB_CTRL_CMD_SIZE: usize = TPM_CRB_ADDR_SIZE - CRB_DATA_BUFFER as usize;
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fn get_fields_map(reg: u32) -> phf::Map<&'static str, [u32; 2]> {
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match reg {
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CRB_LOC_STATE => CRB_LOC_STATE_FIELDS,
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CRB_LOC_STS => CRB_LOC_STS_FIELDS,
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CRB_INTF_ID => CRB_INTF_ID_FIELDS,
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CRB_INTF_ID2 => CRB_INTF_ID2_FIELDS,
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CRB_CTRL_STS => CRB_CTRL_STS_FIELDS,
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_ => {
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2022-12-14 11:41:15 +00:00
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panic!("Fields in '{reg:?}' register were accessed which are Invalid");
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2022-09-12 20:46:03 +00:00
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}
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}
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}
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/// Set a particular field in a Register
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2023-01-24 23:45:10 +00:00
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fn set_reg_field(regs: &mut [u32; TPM_CRB_R_MAX], reg: u32, field: &str, value: u32) {
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2022-09-12 20:46:03 +00:00
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let reg_fields = get_fields_map(reg);
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if reg_fields.contains_key(field) {
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let start = reg_fields.get(field).unwrap()[0];
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let len = reg_fields.get(field).unwrap()[1];
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let mask = (!(0_u32) >> (32 - len)) << start;
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regs[reg as usize] = (regs[reg as usize] & !mask) | ((value << start) & mask);
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} else {
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error!(
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"Failed to tpm Register. {:?} is not a valid field in Reg {:#X}",
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field, reg
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)
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}
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}
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/// Get the value of a particular field in a Register
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2023-01-24 23:45:10 +00:00
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fn get_reg_field(regs: &[u32; TPM_CRB_R_MAX], reg: u32, field: &str) -> u32 {
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let reg_fields = get_fields_map(reg);
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if reg_fields.contains_key(field) {
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let start = reg_fields.get(field).unwrap()[0];
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let len = reg_fields.get(field).unwrap()[1];
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let mask = (!(0_u32) >> (32 - len)) << start;
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(regs[reg as usize] & mask) >> start
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} else {
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// TODO: Sensible return value if fields do not exist
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0x0
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}
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}
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fn locality_from_addr(addr: u32) -> u8 {
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(addr >> 12) as u8
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}
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pub struct Tpm {
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emulator: Emulator,
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cmd: Option<BackendCmd>,
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2023-01-24 23:45:10 +00:00
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regs: [u32; TPM_CRB_R_MAX],
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2022-09-12 20:46:03 +00:00
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backend_buff_size: usize,
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data_buff: [u8; TPM_CRB_BUFFER_MAX],
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data_buff_len: usize,
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}
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impl Tpm {
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pub fn new(path: String) -> Result<Self> {
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let emulator = Emulator::new(path)
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.map_err(|e| Error::Init(anyhow!("Failed while initializing tpm Emulator: {:?}", e)))?;
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let mut tpm = Tpm {
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emulator,
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cmd: None,
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2023-01-24 23:45:10 +00:00
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regs: [0; TPM_CRB_R_MAX],
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2022-09-12 20:46:03 +00:00
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backend_buff_size: TPM_CRB_BUFFER_MAX,
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data_buff: [0; TPM_CRB_BUFFER_MAX],
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data_buff_len: 0,
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};
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tpm.reset()?;
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Ok(tpm)
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}
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fn get_active_locality(&mut self) -> u32 {
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if get_reg_field(&self.regs, CRB_LOC_STATE, "locAssigned") == 0 {
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return TPM_CRB_NO_LOCALITY;
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}
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get_reg_field(&self.regs, CRB_LOC_STATE, "activeLocality")
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}
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fn request_completed(&mut self, result: isize) {
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self.regs[CRB_CTRL_START as usize] = !CRB_START_INVOKE;
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if result != 0 {
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set_reg_field(&mut self.regs, CRB_CTRL_STS, "tpmSts", 1);
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}
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}
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fn reset(&mut self) -> Result<()> {
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let cur_buff_size = self.emulator.get_buffer_size().unwrap();
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2023-01-24 23:45:10 +00:00
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self.regs = [0; TPM_CRB_R_MAX];
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2022-09-12 20:46:03 +00:00
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set_reg_field(&mut self.regs, CRB_LOC_STATE, "tpmRegValidSts", 1);
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set_reg_field(&mut self.regs, CRB_CTRL_STS, "tpmIdle", 1);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"InterfaceType",
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CRB_INTF_TYPE_CRB_ACTIVE,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"InterfaceVersion",
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CRB_INTF_VERSION_CRB,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"CapLocality",
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CRB_INTF_CAP_LOCALITY_0_ONLY,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"CapCRBIdleBypass",
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CRB_INTF_CAP_IDLE_FAST,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"CapDataXferSizeSupport",
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CRB_INTF_CAP_XFER_SIZE_64,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"CapFIFO",
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CRB_INTF_CAP_FIFO_NOT_SUPPORTED,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"CapCRB",
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CRB_INTF_CAP_CRB_SUPPORTED,
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);
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set_reg_field(
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&mut self.regs,
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CRB_INTF_ID,
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"InterfaceSelector",
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CRB_INTF_IF_SELECTOR_CRB,
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);
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set_reg_field(&mut self.regs, CRB_INTF_ID, "RID", 0b0000);
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set_reg_field(&mut self.regs, CRB_INTF_ID2, "VID", PCI_VENDOR_ID_IBM);
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self.regs[CRB_CTRL_CMD_SIZE_REG as usize] = CRB_CTRL_CMD_SIZE as u32;
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self.regs[CRB_CTRL_CMD_LADDR as usize] = TPM_CRB_ADDR_BASE + CRB_DATA_BUFFER;
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self.regs[CRB_CTRL_RSP_SIZE as usize] = CRB_CTRL_CMD_SIZE as u32;
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self.regs[CRB_CTRL_RSP_ADDR as usize] = TPM_CRB_ADDR_BASE + CRB_DATA_BUFFER;
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self.backend_buff_size = cmp::min(cur_buff_size, TPM_CRB_BUFFER_MAX);
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if let Err(e) = self.emulator.startup_tpm(self.backend_buff_size) {
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return Err(Error::Init(anyhow!(
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"Failed while running Startup TPM. Error: {:?}",
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e
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)));
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}
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Ok(())
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}
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}
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//impl BusDevice for TPM
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impl BusDevice for Tpm {
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fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
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let mut offset: u32 = offset as u32;
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let read_len: usize = data.len();
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if offset >= CRB_DATA_BUFFER
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&& (offset + read_len as u32) < (CRB_DATA_BUFFER + self.data_buff.len() as u32)
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{
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// Read from Data Buffer
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let start: usize = (offset as usize) - (CRB_DATA_BUFFER as usize);
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let end: usize = start + read_len;
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data[..].clone_from_slice(&self.data_buff[start..end]);
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} else {
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offset &= 0xff;
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let mut val = self.regs[offset as usize];
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if offset == CRB_LOC_STATE && !self.emulator.get_established_flag() {
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val |= 0x1;
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}
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if data.len() <= 4 {
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data.clone_from_slice(val.to_ne_bytes()[0..read_len].as_ref());
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} else {
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error!(
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"Invalid tpm read: offset {:#X}, data length {:?}",
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offset,
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data.len()
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);
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}
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}
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debug!(
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"MMIO Read: offset {:#X} len {:?} val = {:02X?} ",
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offset,
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data.len(),
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data
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);
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}
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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debug!(
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"MMIO Write: offset {:#X} len {:?} input data {:02X?}",
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offset,
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data.len(),
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data
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);
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let mut offset: u32 = offset as u32;
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if offset < CRB_DATA_BUFFER {
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offset &= 0xff;
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}
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let locality = locality_from_addr(offset) as u32;
|
|
|
|
let write_len = data.len();
|
|
|
|
|
|
|
|
if offset >= CRB_DATA_BUFFER
|
|
|
|
&& (offset + write_len as u32) < (CRB_DATA_BUFFER + self.data_buff.len() as u32)
|
|
|
|
{
|
|
|
|
let start: usize = (offset as usize) - (CRB_DATA_BUFFER as usize);
|
|
|
|
if start == 0 {
|
|
|
|
// If filling data_buff at index 0, reset length to 0
|
|
|
|
self.data_buff_len = 0;
|
|
|
|
self.data_buff.fill(0);
|
|
|
|
}
|
|
|
|
let end: usize = start + data.len();
|
|
|
|
self.data_buff[start..end].clone_from_slice(data);
|
|
|
|
self.data_buff_len += data.len();
|
|
|
|
} else {
|
|
|
|
// Ctrl Commands that take more than 4 bytes as input are not yet supported
|
|
|
|
// CTRL_RSP_ADDR usually gets 8 byte write request. Last 4 bytes are zeros.
|
|
|
|
if write_len > 4 && offset != CRB_CTRL_RSP_ADDR {
|
|
|
|
error!(
|
|
|
|
"Invalid tpm write: offset {:#X}, data length {}",
|
|
|
|
offset,
|
|
|
|
data.len()
|
|
|
|
);
|
|
|
|
return None;
|
|
|
|
}
|
|
|
|
|
|
|
|
let mut input: [u8; 4] = [0; 4];
|
|
|
|
input.copy_from_slice(&data[0..4]);
|
|
|
|
let v = u32::from_le_bytes(input);
|
|
|
|
|
|
|
|
match offset {
|
|
|
|
CRB_CTRL_CMD_SIZE_REG => {
|
|
|
|
self.regs[CRB_CTRL_CMD_SIZE_REG as usize] = v;
|
|
|
|
}
|
|
|
|
CRB_CTRL_CMD_LADDR => {
|
|
|
|
self.regs[CRB_CTRL_CMD_LADDR as usize] = v;
|
|
|
|
}
|
|
|
|
CRB_CTRL_CMD_HADDR => {
|
|
|
|
self.regs[CRB_CTRL_CMD_HADDR as usize] = v;
|
|
|
|
}
|
|
|
|
CRB_CTRL_RSP_SIZE => {
|
|
|
|
self.regs[CRB_CTRL_RSP_SIZE as usize] = v;
|
|
|
|
}
|
|
|
|
CRB_CTRL_RSP_ADDR => {
|
|
|
|
self.regs[CRB_CTRL_RSP_ADDR as usize] = v;
|
|
|
|
}
|
|
|
|
CRB_CTRL_REQ => match v {
|
|
|
|
CRB_CTRL_REQ_CMD_READY => {
|
|
|
|
set_reg_field(&mut self.regs, CRB_CTRL_STS, "tpmIdle", 0);
|
|
|
|
}
|
|
|
|
CRB_CTRL_REQ_GO_IDLE => {
|
|
|
|
set_reg_field(&mut self.regs, CRB_CTRL_STS, "tpmIdle", 1);
|
|
|
|
}
|
|
|
|
_ => {
|
|
|
|
error!("Invalid value passed to CRTL_REQ register");
|
|
|
|
return None;
|
|
|
|
}
|
|
|
|
},
|
|
|
|
CRB_CTRL_CANCEL => {
|
|
|
|
if v == CRB_CANCEL_INVOKE
|
|
|
|
&& (self.regs[CRB_CTRL_START as usize] & CRB_START_INVOKE != 0)
|
|
|
|
{
|
|
|
|
if let Err(e) = self.emulator.cancel_cmd() {
|
|
|
|
error!("Failed to run cancel command. Error: {:?}", e);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
CRB_CTRL_START => {
|
|
|
|
if v == CRB_START_INVOKE
|
|
|
|
&& ((self.regs[CRB_CTRL_START as usize] & CRB_START_INVOKE) == 0)
|
|
|
|
&& self.get_active_locality() == locality
|
|
|
|
{
|
|
|
|
self.regs[CRB_CTRL_START as usize] |= CRB_START_INVOKE;
|
|
|
|
|
|
|
|
self.cmd = Some(BackendCmd {
|
|
|
|
locality: locality as u8,
|
|
|
|
input: self.data_buff[0..self.data_buff_len].to_vec(),
|
|
|
|
input_len: cmp::min(self.data_buff_len, TPM_CRB_BUFFER_MAX),
|
|
|
|
output: self.data_buff.to_vec(),
|
|
|
|
output_len: TPM_CRB_BUFFER_MAX,
|
|
|
|
selftest_done: false,
|
|
|
|
});
|
|
|
|
|
|
|
|
let mut cmd = self.cmd.as_ref().unwrap().clone();
|
|
|
|
let output = self.emulator.deliver_request(&mut cmd).map_err(|e| {
|
|
|
|
Error::DeliverRequest(anyhow!(
|
|
|
|
"Failed to deliver tpm request. Error :{:?}",
|
|
|
|
e
|
|
|
|
))
|
|
|
|
});
|
|
|
|
//TODO: drop the copy here
|
|
|
|
self.data_buff.fill(0);
|
|
|
|
self.data_buff.clone_from_slice(output.unwrap().as_slice());
|
|
|
|
|
|
|
|
self.request_completed(TPM_SUCCESS as isize);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
CRB_LOC_CTRL => {
|
|
|
|
warn!(
|
|
|
|
"CRB_LOC_CTRL locality to write = {:?} val = {:?}",
|
|
|
|
locality, v
|
|
|
|
);
|
|
|
|
match v {
|
|
|
|
CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT => {}
|
|
|
|
CRB_LOC_CTRL_RELINQUISH => {
|
|
|
|
set_reg_field(&mut self.regs, CRB_LOC_STATE, "locAssigned", 0);
|
|
|
|
set_reg_field(&mut self.regs, CRB_LOC_STS, "Granted", 0);
|
|
|
|
}
|
|
|
|
CRB_LOC_CTRL_REQUEST_ACCESS => {
|
|
|
|
set_reg_field(&mut self.regs, CRB_LOC_STS, "Granted", 1);
|
|
|
|
set_reg_field(&mut self.regs, CRB_LOC_STS, "beenSeized", 0);
|
|
|
|
set_reg_field(&mut self.regs, CRB_LOC_STATE, "locAssigned", 1);
|
|
|
|
}
|
|
|
|
_ => {
|
|
|
|
error!("Invalid value to write in CRB_LOC_CTRL {:#X} ", v);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
_ => {
|
|
|
|
error!(
|
|
|
|
"Invalid tpm write: offset {:#X}, data length {:?}",
|
|
|
|
offset,
|
|
|
|
data.len()
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
None
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(test)]
|
|
|
|
mod tests {
|
|
|
|
use super::*;
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
fn test_set_get_reg_field() {
|
2023-01-24 23:45:10 +00:00
|
|
|
let mut regs: [u32; TPM_CRB_R_MAX] = [0; TPM_CRB_R_MAX];
|
2022-09-12 20:46:03 +00:00
|
|
|
set_reg_field(&mut regs, CRB_INTF_ID, "RID", 0xAC);
|
|
|
|
assert_eq!(
|
|
|
|
get_reg_field(®s, CRB_INTF_ID, "RID"),
|
|
|
|
0xAC,
|
|
|
|
concat!("Test: ", stringify!(set_get_reg_field))
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|