cloud-hypervisor/pci/Cargo.toml

[package]
name = "pci"
version = "0.1.0"
authors = ["Samuel Ortiz <sameo@linux.intel.com>"]
edition = "2018"

[dependencies]
vm-allocator = { path = "../vm-allocator" }
byteorder = "*"
devices = { path = "../devices" }
kvm-bindings = "0.1"
kvm-ioctls = { git = "https://github.com/rust-vmm/kvm-ioctls", branch = "master" }
libc = ">=0.2.39"
log = "*"
vm-memory = { git = "https://github.com/rust-vmm/vm-memory" }
vmm-sys-util = { git = "https://github.com/rust-vmm/vmm-sys-util" }
pci: Add minimal PCI host emulation crate This crate is based on the crosvm devices/src/pci implementation from 107edb3e We introduced a few changes: - This one is a standalone crate. The device crate does not carry any PCI specific bits. - Simplified PCI root configuration. We only carry a pointer to a PciConfiguration, not a wrapper around it. - Simplified BAR allocation API. All BARs from the PciDevice instance must be generated at once through the PciDevice.allocate_bars() method. - The PCI BARs are added to the MMIO bus from the PciRoot add_device() method. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com> 2019-04-18 11:59:12 +02:00			`[package]`
			`name = "pci"`
			`version = "0.1.0"`
			`authors = ["Samuel Ortiz <sameo@linux.intel.com>"]`
			`edition = "2018"`

			`[dependencies]`
			`vm-allocator = { path = "../vm-allocator" }`
			`byteorder = "*"`
			`devices = { path = "../devices" }`
			`kvm-bindings = "0.1"`
dep: Rely on latest kvm-ioctls crate In order to have access to the newly added signal_msi() function from the kvm-ioctls crate, this commit updates the version of the kvm-ioctls to the latest one. Because set_user_memory_region() has been swtiched to "unsafe", we also need to handle this small change in our cloud-hypervisor code directly. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> 2019-06-03 14:09:01 -07:00			`kvm-ioctls = { git = "https://github.com/rust-vmm/kvm-ioctls", branch = "master" }`
pci: Add minimal PCI host emulation crate This crate is based on the crosvm devices/src/pci implementation from 107edb3e We introduced a few changes: - This one is a standalone crate. The device crate does not carry any PCI specific bits. - Simplified PCI root configuration. We only carry a pointer to a PciConfiguration, not a wrapper around it. - Simplified BAR allocation API. All BARs from the PciDevice instance must be generated at once through the PciDevice.allocate_bars() method. - The PCI BARs are added to the MMIO bus from the PciRoot add_device() method. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com> 2019-04-18 11:59:12 +02:00			`libc = ">=0.2.39"`
			`log = "*"`
			`vm-memory = { git = "https://github.com/rust-vmm/vm-memory" }`
vendor: Move to the rust-vmm vmm-sys-util package Locked to 60fe35be but no longer dependent on liujing2 repo. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com> 2019-06-04 13:23:52 +02:00			`vmm-sys-util = { git = "https://github.com/rust-vmm/vmm-sys-util" }`