2019-02-25 21:53:01 +00:00
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// Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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2019-05-08 10:22:53 +00:00
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// found in the LICENSE-BSD-3-Clause file.
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2019-02-25 21:53:01 +00:00
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use std::{io, mem, result};
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use super::gdt::{gdt_entry, kvm_segment_from_gdt};
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use arch_gen::x86::msr_index;
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use kvm_bindings::{kvm_fpu, kvm_msr_entry, kvm_msrs, kvm_regs, kvm_sregs};
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use kvm_ioctls::VcpuFd;
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use layout::{BOOT_GDT_START, BOOT_IDT_START, PDE_START, PDPTE_START, PML4_START};
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use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryMmap};
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2019-02-25 21:53:01 +00:00
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2019-08-01 15:19:38 +00:00
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// MTRR constants
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const MTRR_ENABLE: u64 = 0x800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
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const MTRR_MEM_TYPE_WB: u64 = 0x6;
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2019-02-25 21:53:01 +00:00
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#[derive(Debug)]
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pub enum Error {
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/// Failed to get SREGs for this CPU.
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GetStatusRegisters(io::Error),
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/// Failed to set base registers for this CPU.
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SetBaseRegisters(io::Error),
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/// Failed to configure the FPU.
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SetFPURegisters(io::Error),
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/// Setting up MSRs failed.
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SetModelSpecificRegisters(io::Error),
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/// Failed to set SREGs for this CPU.
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SetStatusRegisters(io::Error),
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/// Writing the GDT to RAM failed.
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WriteGDT,
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/// Writing the IDT to RAM failed.
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WriteIDT,
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/// Writing PDPTE to RAM failed.
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WritePDPTEAddress,
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/// Writing PDE to RAM failed.
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WritePDEAddress,
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/// Writing PML4 to RAM failed.
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WritePML4Address,
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}
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pub type Result<T> = result::Result<T, Error>;
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/// Configure Floating-Point Unit (FPU) registers for a given CPU.
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///
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/// # Arguments
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///
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/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
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pub fn setup_fpu(vcpu: &VcpuFd) -> Result<()> {
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let fpu: kvm_fpu = kvm_fpu {
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fcw: 0x37f,
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mxcsr: 0x1f80,
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..Default::default()
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};
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vcpu.set_fpu(&fpu).map_err(Error::SetFPURegisters)
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}
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/// Configure Model Specific Registers (MSRs) for a given CPU.
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///
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/// # Arguments
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///
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/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
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pub fn setup_msrs(vcpu: &VcpuFd) -> Result<()> {
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let entry_vec = create_msr_entries();
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let vec_size_bytes =
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mem::size_of::<kvm_msrs>() + (entry_vec.len() * mem::size_of::<kvm_msr_entry>());
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let vec: Vec<u8> = Vec::with_capacity(vec_size_bytes);
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let msrs: &mut kvm_msrs = unsafe {
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// Converting the vector's memory to a struct is unsafe. Carefully using the read-only
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// vector to size and set the members ensures no out-of-bounds errors below.
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&mut *(vec.as_ptr() as *mut kvm_msrs)
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};
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unsafe {
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// Mapping the unsized array to a slice is unsafe because the length isn't known.
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// Providing the length used to create the struct guarantees the entire slice is valid.
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let entries: &mut [kvm_msr_entry] = msrs.entries.as_mut_slice(entry_vec.len());
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entries.copy_from_slice(&entry_vec);
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}
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msrs.nmsrs = entry_vec.len() as u32;
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vcpu.set_msrs(msrs)
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.map_err(Error::SetModelSpecificRegisters)
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}
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/// Configure base registers for a given CPU.
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///
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/// # Arguments
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///
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/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
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/// * `boot_ip` - Starting instruction pointer.
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/// * `boot_sp` - Starting stack pointer.
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/// * `boot_si` - Must point to zero page address per Linux ABI.
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pub fn setup_regs(vcpu: &VcpuFd, boot_ip: u64, boot_sp: u64, boot_si: u64) -> Result<()> {
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let regs: kvm_regs = kvm_regs {
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rflags: 0x0000000000000002u64,
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rip: boot_ip,
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rsp: boot_sp,
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rbp: boot_sp,
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rsi: boot_si,
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..Default::default()
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};
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vcpu.set_regs(®s).map_err(Error::SetBaseRegisters)
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}
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/// Configures the segment registers and system page tables for a given CPU.
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///
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/// # Arguments
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///
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/// * `mem` - The memory that will be passed to the guest.
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/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
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pub fn setup_sregs(mem: &GuestMemoryMmap, vcpu: &VcpuFd) -> Result<()> {
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let mut sregs: kvm_sregs = vcpu.get_sregs().map_err(Error::GetStatusRegisters)?;
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configure_segments_and_sregs(mem, &mut sregs)?;
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setup_page_tables(mem, &mut sregs)?; // TODO(dgreid) - Can this be done once per system instead?
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vcpu.set_sregs(&sregs).map_err(Error::SetStatusRegisters)
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}
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const BOOT_GDT_MAX: usize = 4;
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const EFER_LMA: u64 = 0x400;
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const EFER_LME: u64 = 0x100;
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const X86_CR0_PE: u64 = 0x1;
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const X86_CR0_PG: u64 = 0x80000000;
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const X86_CR4_PAE: u64 = 0x20;
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fn write_gdt_table(table: &[u64], guest_mem: &GuestMemoryMmap) -> Result<()> {
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let boot_gdt_addr = BOOT_GDT_START;
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for (index, entry) in table.iter().enumerate() {
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let addr = guest_mem
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.checked_offset(boot_gdt_addr, index * mem::size_of::<u64>())
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.ok_or(Error::WriteGDT)?;
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guest_mem
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.write_obj(*entry, addr)
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.map_err(|_| Error::WriteGDT)?;
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}
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Ok(())
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}
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fn write_idt_value(val: u64, guest_mem: &GuestMemoryMmap) -> Result<()> {
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let boot_idt_addr = BOOT_IDT_START;
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guest_mem
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.write_obj(val, boot_idt_addr)
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.map_err(|_| Error::WriteIDT)
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}
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fn configure_segments_and_sregs(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) -> Result<()> {
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let gdt_table: [u64; BOOT_GDT_MAX as usize] = [
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gdt_entry(0, 0, 0), // NULL
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gdt_entry(0xa09b, 0, 0xfffff), // CODE
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gdt_entry(0xc093, 0, 0xfffff), // DATA
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gdt_entry(0x808b, 0, 0xfffff), // TSS
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];
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let code_seg = kvm_segment_from_gdt(gdt_table[1], 1);
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let data_seg = kvm_segment_from_gdt(gdt_table[2], 2);
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let tss_seg = kvm_segment_from_gdt(gdt_table[3], 3);
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// Write segments
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write_gdt_table(&gdt_table[..], mem)?;
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sregs.gdt.base = BOOT_GDT_START.raw_value();
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sregs.gdt.limit = mem::size_of_val(&gdt_table) as u16 - 1;
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write_idt_value(0, mem)?;
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sregs.idt.base = BOOT_IDT_START.raw_value();
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sregs.idt.limit = mem::size_of::<u64>() as u16 - 1;
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sregs.cs = code_seg;
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sregs.ds = data_seg;
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sregs.es = data_seg;
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sregs.fs = data_seg;
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sregs.gs = data_seg;
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sregs.ss = data_seg;
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sregs.tr = tss_seg;
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/* 64-bit protected mode */
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sregs.cr0 |= X86_CR0_PE;
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sregs.efer |= EFER_LME | EFER_LMA;
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Ok(())
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}
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fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) -> Result<()> {
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// Puts PML4 right after zero page but aligned to 4k.
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// Entry covering VA [0..512GB)
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mem.write_obj(PDPTE_START.raw_value() | 0x03, PML4_START)
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.map_err(|_| Error::WritePML4Address)?;
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// Entry covering VA [0..1GB)
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mem.write_obj(PDE_START.raw_value() | 0x03, PDPTE_START)
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.map_err(|_| Error::WritePDPTEAddress)?;
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// 512 2MB entries together covering VA [0..1GB). Note we are assuming
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// CPU supports 2MB pages (/proc/cpuinfo has 'pse'). All modern CPUs do.
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for i in 0..512 {
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mem.write_obj((i << 21) + 0x83u64, PDE_START.unchecked_add(i * 8))
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.map_err(|_| Error::WritePDEAddress)?;
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}
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sregs.cr3 = PML4_START.raw_value();
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sregs.cr4 |= X86_CR4_PAE;
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sregs.cr0 |= X86_CR0_PG;
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Ok(())
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}
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fn create_msr_entries() -> Vec<kvm_msr_entry> {
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let mut entries = Vec::<kvm_msr_entry>::new();
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_IA32_SYSENTER_CS,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_IA32_SYSENTER_ESP,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_IA32_SYSENTER_EIP,
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data: 0x0,
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..Default::default()
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});
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// x86_64 specific msrs, we only run on x86_64 not x86.
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_STAR,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_CSTAR,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_KERNEL_GS_BASE,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_SYSCALL_MASK,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_LSTAR,
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data: 0x0,
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..Default::default()
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});
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// end of x86_64 specific code
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_IA32_TSC,
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data: 0x0,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_IA32_MISC_ENABLE,
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data: msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64,
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..Default::default()
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});
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entries.push(kvm_msr_entry {
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index: msr_index::MSR_MTRRdefType,
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data: MTRR_ENABLE | MTRR_MEM_TYPE_WB,
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..Default::default()
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});
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entries
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}
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#[cfg(test)]
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mod tests {
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extern crate kvm_ioctls;
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extern crate vm_memory;
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use super::*;
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use kvm_ioctls::Kvm;
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use vm_memory::{GuestAddress, GuestMemoryMmap};
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fn create_guest_mem() -> GuestMemoryMmap {
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GuestMemoryMmap::new(&vec![(GuestAddress(0), 0x10000)]).unwrap()
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}
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fn read_u64(gm: &GuestMemoryMmap, offset: GuestAddress) -> u64 {
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gm.read_obj(offset).unwrap()
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}
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#[test]
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fn segments_and_sregs() {
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let mut sregs: kvm_sregs = Default::default();
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let gm = create_guest_mem();
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configure_segments_and_sregs(&gm, &mut sregs).unwrap();
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assert_eq!(0x0, read_u64(&gm, BOOT_GDT_START));
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assert_eq!(
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0xaf9b000000ffff,
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read_u64(&gm, BOOT_GDT_START.unchecked_add(8))
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);
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assert_eq!(
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0xcf93000000ffff,
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read_u64(&gm, BOOT_GDT_START.unchecked_add(16))
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);
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assert_eq!(
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0x8f8b000000ffff,
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read_u64(&gm, BOOT_GDT_START.unchecked_add(24))
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);
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assert_eq!(0x0, read_u64(&gm, BOOT_IDT_START));
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assert_eq!(0, sregs.cs.base);
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assert_eq!(0xfffff, sregs.ds.limit);
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assert_eq!(0x10, sregs.es.selector);
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assert_eq!(1, sregs.fs.present);
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assert_eq!(1, sregs.gs.g);
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assert_eq!(0, sregs.ss.avl);
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assert_eq!(0, sregs.tr.base);
|
|
|
|
assert_eq!(0xfffff, sregs.tr.limit);
|
|
|
|
assert_eq!(0, sregs.tr.avl);
|
|
|
|
assert_eq!(X86_CR0_PE, sregs.cr0);
|
|
|
|
assert_eq!(EFER_LME | EFER_LMA, sregs.efer);
|
|
|
|
}
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
fn page_tables() {
|
|
|
|
let mut sregs: kvm_sregs = Default::default();
|
|
|
|
let gm = create_guest_mem();
|
|
|
|
setup_page_tables(&gm, &mut sregs).unwrap();
|
|
|
|
|
|
|
|
assert_eq!(0xa003, read_u64(&gm, PML4_START));
|
|
|
|
assert_eq!(0xb003, read_u64(&gm, PDPTE_START));
|
|
|
|
for i in 0..512 {
|
|
|
|
assert_eq!(
|
|
|
|
(i << 21) + 0x83u64,
|
|
|
|
read_u64(&gm, PDE_START.unchecked_add(i * 8))
|
|
|
|
);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert_eq!(PML4_START.raw_value(), sregs.cr3);
|
|
|
|
assert_eq!(X86_CR4_PAE, sregs.cr4);
|
|
|
|
assert_eq!(X86_CR0_PG, sregs.cr0);
|
|
|
|
}
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
fn test_setup_fpu() {
|
|
|
|
let kvm = Kvm::new().unwrap();
|
|
|
|
let vm = kvm.create_vm().unwrap();
|
|
|
|
let vcpu = vm.create_vcpu(0).unwrap();
|
|
|
|
setup_fpu(&vcpu).unwrap();
|
|
|
|
|
|
|
|
let expected_fpu: kvm_fpu = kvm_fpu {
|
|
|
|
fcw: 0x37f,
|
|
|
|
mxcsr: 0x1f80,
|
|
|
|
..Default::default()
|
|
|
|
};
|
|
|
|
let actual_fpu: kvm_fpu = vcpu.get_fpu().unwrap();
|
|
|
|
// TODO: auto-generate kvm related structures with PartialEq on.
|
|
|
|
assert_eq!(expected_fpu.fcw, actual_fpu.fcw);
|
|
|
|
// Setting the mxcsr register from kvm_fpu inside setup_fpu does not influence anything.
|
|
|
|
// See 'kvm_arch_vcpu_ioctl_set_fpu' from arch/x86/kvm/x86.c.
|
|
|
|
// The mxcsr will stay 0 and the assert below fails. Decide whether or not we should
|
|
|
|
// remove it at all.
|
|
|
|
// assert!(expected_fpu.mxcsr == actual_fpu.mxcsr);
|
|
|
|
}
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
fn test_setup_msrs() {
|
|
|
|
let kvm = Kvm::new().unwrap();
|
|
|
|
let vm = kvm.create_vm().unwrap();
|
|
|
|
let vcpu = vm.create_vcpu(0).unwrap();
|
|
|
|
setup_msrs(&vcpu).unwrap();
|
|
|
|
|
|
|
|
// This test will check against the last MSR entry configured (the tenth one).
|
|
|
|
// See create_msr_entries for details.
|
|
|
|
let test_kvm_msrs_entry = [kvm_msr_entry {
|
|
|
|
index: msr_index::MSR_IA32_MISC_ENABLE,
|
|
|
|
..Default::default()
|
|
|
|
}];
|
|
|
|
let vec_size_bytes = mem::size_of::<kvm_msrs>() + mem::size_of::<kvm_msr_entry>();
|
|
|
|
let vec: Vec<u8> = Vec::with_capacity(vec_size_bytes);
|
|
|
|
let mut msrs: &mut kvm_msrs = unsafe {
|
|
|
|
// Converting the vector's memory to a struct is unsafe. Carefully using the read-only
|
|
|
|
// vector to size and set the members ensures no out-of-bounds errors below.
|
|
|
|
&mut *(vec.as_ptr() as *mut kvm_msrs)
|
|
|
|
};
|
|
|
|
|
|
|
|
unsafe {
|
|
|
|
let entries: &mut [kvm_msr_entry] = msrs.entries.as_mut_slice(1);
|
|
|
|
entries.copy_from_slice(&test_kvm_msrs_entry);
|
|
|
|
}
|
|
|
|
|
|
|
|
msrs.nmsrs = 1;
|
|
|
|
// get_msrs returns the number of msrs that it succeed in reading. We only want to read 1
|
|
|
|
// in this test case scenario.
|
|
|
|
let read_msrs = vcpu.get_msrs(&mut msrs).unwrap();
|
|
|
|
assert_eq!(read_msrs, 1);
|
|
|
|
|
|
|
|
// Official entries that were setup when we did setup_msrs. We need to assert that the
|
|
|
|
// tenth one (i.e the one with index msr_index::MSR_IA32_MISC_ENABLE has the data we
|
|
|
|
// expect.
|
|
|
|
let entry_vec = create_msr_entries();
|
|
|
|
unsafe {
|
|
|
|
assert_eq!(entry_vec[9], msrs.entries.as_slice(1)[0]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
fn test_setup_regs() {
|
|
|
|
let kvm = Kvm::new().unwrap();
|
|
|
|
let vm = kvm.create_vm().unwrap();
|
|
|
|
let vcpu = vm.create_vcpu(0).unwrap();
|
|
|
|
|
|
|
|
let expected_regs: kvm_regs = kvm_regs {
|
|
|
|
rflags: 0x0000000000000002u64,
|
|
|
|
rip: 1,
|
|
|
|
rsp: 2,
|
|
|
|
rbp: 2,
|
|
|
|
rsi: 3,
|
|
|
|
..Default::default()
|
|
|
|
};
|
|
|
|
|
|
|
|
setup_regs(
|
|
|
|
&vcpu,
|
|
|
|
expected_regs.rip,
|
|
|
|
expected_regs.rsp,
|
|
|
|
expected_regs.rsi,
|
|
|
|
)
|
|
|
|
.unwrap();
|
|
|
|
|
|
|
|
let actual_regs: kvm_regs = vcpu.get_regs().unwrap();
|
|
|
|
assert_eq!(actual_regs, expected_regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
fn test_setup_sregs() {
|
|
|
|
let kvm = Kvm::new().unwrap();
|
|
|
|
let vm = kvm.create_vm().unwrap();
|
|
|
|
let vcpu = vm.create_vcpu(0).unwrap();
|
|
|
|
|
|
|
|
let mut expected_sregs: kvm_sregs = vcpu.get_sregs().unwrap();
|
|
|
|
let gm = create_guest_mem();
|
|
|
|
configure_segments_and_sregs(&gm, &mut expected_sregs).unwrap();
|
|
|
|
setup_page_tables(&gm, &mut expected_sregs).unwrap();
|
|
|
|
|
|
|
|
setup_sregs(&gm, &vcpu).unwrap();
|
|
|
|
let actual_sregs: kvm_sregs = vcpu.get_sregs().unwrap();
|
|
|
|
assert_eq!(expected_sregs, actual_sregs);
|
|
|
|
}
|
|
|
|
}
|