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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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acpi: Refactor create_acpi_tables()
Split the code of create_acpi_tables() into multiple functions for easy extension in future. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
This commit is contained in:
Michael Zhao
Sebastien Boeuf
parent
5ae04349da
commit
01acea3102
163
vmm/src/acpi.rs
163
vmm/src/acpi.rs
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@ -105,74 +105,44 @@ pub fn create_dsdt_table(
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dsdt
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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numa_nodes: &NumaNodes,
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) -> GuestAddress {
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let rsdp_offset = arch::layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(device_manager, cpu_manager, memory_manager);
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let dsdt_offset = rsdp_offset.checked_add(Rsdp::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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fn create_facp_table(dsdt_offset: GuestAddress) -> Sdt {
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = Sdt::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// PM_TMR_BLK I/O port
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// x86_64 specific fields
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#[cfg(target_arch = "x86_64")]
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{
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// PM_TMR_BLK I/O port
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facp.write(76, 0xb008u32);
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// RESET_REG
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facp.write(116, GenericAddress::io_port_address::<u8>(0x3c0));
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// RESET_VALUE
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facp.write(128, 1u8);
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// X_PM_TMR_BLK
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facp.write(208, GenericAddress::io_port_address::<u32>(0xb008));
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// SLEEP_CONTROL_REG
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facp.write(244, GenericAddress::io_port_address::<u8>(0x3c0));
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// SLEEP_STATUS_REG
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facp.write(256, GenericAddress::io_port_address::<u8>(0x3c0));
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}
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// Architecture common fields
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// HW_REDUCED_ACPI, RESET_REG_SUP, TMR_VAL_EXT
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let fadt_flags: u32 = 1 << 20 | 1 << 10 | 1 << 8;
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facp.write(112, fadt_flags);
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// RESET_REG
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#[cfg(target_arch = "x86_64")]
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facp.write(116, GenericAddress::io_port_address::<u8>(0x3c0));
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// RESET_VALUE
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#[cfg(target_arch = "x86_64")]
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facp.write(128, 1u8);
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facp.write(131, 3u8); // FADT minor version
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facp.write(140, dsdt_offset.0); // X_DSDT
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// X_PM_TMR_BLK
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#[cfg(target_arch = "x86_64")]
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facp.write(208, GenericAddress::io_port_address::<u32>(0xb008));
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// SLEEP_CONTROL_REG
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#[cfg(target_arch = "x86_64")]
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facp.write(244, GenericAddress::io_port_address::<u8>(0x3c0));
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// SLEEP_STATUS_REG
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#[cfg(target_arch = "x86_64")]
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facp.write(256, GenericAddress::io_port_address::<u8>(0x3c0));
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facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity
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// FADT minor version
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facp.write(131, 3u8);
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// X_DSDT
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facp.write(140, dsdt_offset.0);
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// Hypervisor Vendor Identity
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facp.write(268, b"CLOUDHYP");
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facp.update_checksum();
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let madt = cpu_manager.lock().unwrap().create_madt();
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
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guest_mem
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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facp
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}
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// MCFG
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fn create_mcfg_table() -> Sdt {
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let mut mcfg = Sdt::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
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// MCFG reserved 8 bytes
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@ -186,19 +156,10 @@ pub fn create_acpi_tables(
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end: 0,
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..Default::default()
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});
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mcfg
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}
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let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
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guest_mem
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.write_slice(mcfg.as_slice(), mcfg_offset)
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.expect("Error writing MCFG table");
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tables.push(mcfg_offset.0);
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// SRAT and SLIT
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// Only created if the NUMA nodes list is not empty.
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let (prev_tbl_len, prev_tbl_off) = if numa_nodes.is_empty() {
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(mcfg.len(), mcfg_offset)
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} else {
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// SRAT
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fn create_srat_table(numa_nodes: &NumaNodes) -> Sdt {
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let mut srat = Sdt::new(*b"SRAT", 36, 3, *b"CLOUDH", *b"CHSRAT ", 1);
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// SRAT reserved 12 bytes
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srat.append_slice(&[0u8; 12]);
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@ -245,14 +206,10 @@ pub fn create_acpi_tables(
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});
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}
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}
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srat
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}
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let srat_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
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guest_mem
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.write_slice(srat.as_slice(), srat_offset)
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.expect("Error writing SRAT table");
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tables.push(srat_offset.0);
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// SLIT
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fn create_slit_table(numa_nodes: &NumaNodes) -> Sdt {
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let mut slit = Sdt::new(*b"SLIT", 36, 1, *b"CLOUDH", *b"CHSLIT ", 1);
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// Number of System Localities on 8 bytes.
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slit.append(numa_nodes.len() as u64);
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@ -272,7 +229,65 @@ pub fn create_acpi_tables(
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slit.append(dist);
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}
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}
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slit
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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numa_nodes: &NumaNodes,
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) -> GuestAddress {
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let rsdp_offset = arch::layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(device_manager, cpu_manager, memory_manager);
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let dsdt_offset = rsdp_offset.checked_add(Rsdp::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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let facp = create_facp_table(dsdt_offset);
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let madt = cpu_manager.lock().unwrap().create_madt();
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
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guest_mem
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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// MCFG
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let mcfg = create_mcfg_table();
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let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
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guest_mem
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.write_slice(mcfg.as_slice(), mcfg_offset)
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.expect("Error writing MCFG table");
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tables.push(mcfg_offset.0);
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// SRAT and SLIT
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// Only created if the NUMA nodes list is not empty.
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let (prev_tbl_len, prev_tbl_off) = if numa_nodes.is_empty() {
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(mcfg.len(), mcfg_offset)
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} else {
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// SRAT
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let srat = create_srat_table(numa_nodes);
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let srat_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
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guest_mem
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.write_slice(srat.as_slice(), srat_offset)
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.expect("Error writing SRAT table");
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tables.push(srat_offset.0);
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// SLIT
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let slit = create_slit_table(numa_nodes);
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let slit_offset = srat_offset.checked_add(srat.len() as u64).unwrap();
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guest_mem
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.write_slice(slit.as_slice(), slit_offset)
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