From 080ce9b0682582ce81929c0961d9c0ff7156e571 Mon Sep 17 00:00:00 2001
From: Rob Bradford <robert.bradford@intel.com>
Date: Tue, 5 Oct 2021 15:06:55 +0100
Subject: [PATCH] vmm: Populate MCFG table with details of all PCI segments

The MCFG table holds the PCI MMIO config details for all the MMIO PCI
config devices.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
---
 vmm/src/acpi.rs           | 22 ++++++++++++----------
 vmm/src/device_manager.rs |  5 +++++
 vmm/src/pci_segment.rs    |  4 ++--
 3 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/vmm/src/acpi.rs b/vmm/src/acpi.rs
index 679d92a04..7106aa2af 100644
--- a/vmm/src/acpi.rs
+++ b/vmm/src/acpi.rs
@@ -222,20 +222,22 @@ fn create_facp_table(dsdt_offset: GuestAddress) -> Sdt {
     facp
 }
 
-fn create_mcfg_table() -> Sdt {
+fn create_mcfg_table(device_manager: &Arc<Mutex<DeviceManager>>) -> Sdt {
     let mut mcfg = Sdt::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG  ", 1);
 
     // MCFG reserved 8 bytes
     mcfg.append(0u64);
 
-    // 32-bit PCI enhanced configuration mechanism
-    mcfg.append(PciRangeEntry {
-        base_address: arch::layout::PCI_MMCONFIG_START.0,
-        segment: 0,
-        start: 0,
-        end: 0,
-        ..Default::default()
-    });
+    for segment in device_manager.lock().unwrap().pci_segments() {
+        // 32-bit PCI enhanced configuration mechanism
+        mcfg.append(PciRangeEntry {
+            base_address: segment.mmio_config_address,
+            segment: segment.id,
+            start: 0,
+            end: 0,
+            ..Default::default()
+        });
+    }
     mcfg
 }
 
@@ -536,7 +538,7 @@ pub fn create_acpi_tables(
     }
 
     // MCFG
-    let mcfg = create_mcfg_table();
+    let mcfg = create_mcfg_table(device_manager);
     let mcfg_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
     guest_mem
         .write_slice(mcfg.as_slice(), mcfg_offset)
diff --git a/vmm/src/device_manager.rs b/vmm/src/device_manager.rs
index 3af27a341..a3d60d99e 100644
--- a/vmm/src/device_manager.rs
+++ b/vmm/src/device_manager.rs
@@ -3265,6 +3265,11 @@ impl DeviceManager {
         Arc::clone(self.pci_segments[0].pci_config_io.as_ref().unwrap())
     }
 
+    #[cfg(feature = "acpi")]
+    pub(crate) fn pci_segments(&self) -> &Vec<PciSegment> {
+        &self.pci_segments
+    }
+
     pub fn console(&self) -> &Arc<Console> {
         &self.console
     }
diff --git a/vmm/src/pci_segment.rs b/vmm/src/pci_segment.rs
index 905364846..674007fe3 100644
--- a/vmm/src/pci_segment.rs
+++ b/vmm/src/pci_segment.rs
@@ -25,10 +25,10 @@ use vm_device::BusDevice;
 const PCI_MMIO_CONFIG_SIZE: u64 = 4096 * 256;
 
 pub(crate) struct PciSegment {
-    id: u16,
+    pub(crate) id: u16,
     pub(crate) pci_bus: Arc<Mutex<PciBus>>,
     pub(crate) pci_config_mmio: Arc<Mutex<PciConfigMmio>>,
-    mmio_config_address: u64,
+    pub(crate) mmio_config_address: u64,
 
     #[cfg(target_arch = "x86_64")]
     pub(crate) pci_config_io: Option<Arc<Mutex<PciConfigIo>>>,