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arch, vmm: Clear AMX CPUID bits if the feature is not enabled
Fixes: #5833 Signed-off-by: Bo Chen <chen.bo@intel.com>
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@ -37,6 +37,9 @@ const TSC_DEADLINE_TIMER_ECX_BIT: u8 = 24; // tsc deadline timer ecx bit.
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const HYPERVISOR_ECX_BIT: u8 = 31; // Hypervisor ecx bit.
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const HYPERVISOR_ECX_BIT: u8 = 31; // Hypervisor ecx bit.
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const MTRR_EDX_BIT: u8 = 12; // Hypervisor ecx bit.
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const MTRR_EDX_BIT: u8 = 12; // Hypervisor ecx bit.
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const INVARIANT_TSC_EDX_BIT: u8 = 8; // Invariant TSC bit on 0x8000_0007 EDX
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const INVARIANT_TSC_EDX_BIT: u8 = 8; // Invariant TSC bit on 0x8000_0007 EDX
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const AMX_BF16: u8 = 22; // AMX tile computation on bfloat16 numbers
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const AMX_TILE: u8 = 24; // AMX tile load/store instructions
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const AMX_INT8: u8 = 25; // AMX tile computation on 8-bit integers
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// KVM feature bits
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// KVM feature bits
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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@ -151,6 +154,7 @@ pub struct CpuidConfig {
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pub kvm_hyperv: bool,
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pub kvm_hyperv: bool,
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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pub tdx: bool,
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pub tdx: bool,
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pub amx: bool,
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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@ -640,6 +644,12 @@ pub fn generate_common_cpuid(
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// Update some existing CPUID
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// Update some existing CPUID
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for entry in cpuid.as_mut_slice().iter_mut() {
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for entry in cpuid.as_mut_slice().iter_mut() {
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match entry.function {
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match entry.function {
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// Clear AMX related bits if the AMX feature is not enabled
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0x7 => {
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if !config.amx && entry.index == 0 {
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entry.edx &= !(1 << AMX_BF16 | 1 << AMX_TILE | 1 << AMX_INT8)
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}
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}
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0xd =>
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0xd =>
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{
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{
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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@ -745,6 +745,7 @@ impl CpuManager {
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kvm_hyperv: self.config.kvm_hyperv,
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kvm_hyperv: self.config.kvm_hyperv,
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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tdx,
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tdx,
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amx: self.config.features.amx,
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},
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},
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)
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)
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.map_err(Error::CommonCpuId)?
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.map_err(Error::CommonCpuId)?
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@ -1665,6 +1665,7 @@ impl Vmm {
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let common_cpuid = {
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let common_cpuid = {
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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let tdx = vm_config.lock().unwrap().is_tdx_enabled();
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let tdx = vm_config.lock().unwrap().is_tdx_enabled();
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let amx = vm_config.lock().unwrap().cpus.features.amx;
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let phys_bits =
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let phys_bits =
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vm::physical_bits(&hypervisor, vm_config.lock().unwrap().cpus.max_phys_bits);
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vm::physical_bits(&hypervisor, vm_config.lock().unwrap().cpus.max_phys_bits);
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arch::generate_common_cpuid(
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arch::generate_common_cpuid(
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@ -1675,6 +1676,7 @@ impl Vmm {
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kvm_hyperv: vm_config.lock().unwrap().cpus.kvm_hyperv,
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kvm_hyperv: vm_config.lock().unwrap().cpus.kvm_hyperv,
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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tdx,
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tdx,
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amx,
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},
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},
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)
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)
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.map_err(|e| {
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.map_err(|e| {
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@ -1866,6 +1868,7 @@ impl Vmm {
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kvm_hyperv: vm_config.cpus.kvm_hyperv,
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kvm_hyperv: vm_config.cpus.kvm_hyperv,
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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tdx: vm_config.is_tdx_enabled(),
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tdx: vm_config.is_tdx_enabled(),
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amx: vm_config.cpus.features.amx,
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},
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},
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)
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)
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.map_err(|e| {
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.map_err(|e| {
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@ -2409,6 +2409,7 @@ impl Snapshottable for Vm {
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#[cfg(all(feature = "kvm", target_arch = "x86_64"))]
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#[cfg(all(feature = "kvm", target_arch = "x86_64"))]
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let common_cpuid = {
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let common_cpuid = {
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let amx = self.config.lock().unwrap().cpus.features.amx;
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let phys_bits = physical_bits(
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let phys_bits = physical_bits(
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&self.hypervisor,
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&self.hypervisor,
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self.config.lock().unwrap().cpus.max_phys_bits,
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self.config.lock().unwrap().cpus.max_phys_bits,
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@ -2421,6 +2422,7 @@ impl Snapshottable for Vm {
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kvm_hyperv: self.config.lock().unwrap().cpus.kvm_hyperv,
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kvm_hyperv: self.config.lock().unwrap().cpus.kvm_hyperv,
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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tdx: tdx_enabled,
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tdx: tdx_enabled,
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amx,
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},
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},
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)
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)
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.map_err(|e| {
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.map_err(|e| {
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