pci: Export network and mass storage sub classes

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Samuel Ortiz 2019-07-02 17:08:51 +02:00
parent 49d6b495d5
commit 0b7fb42a6c
2 changed files with 46 additions and 2 deletions

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@ -124,6 +124,50 @@ impl PciSubclass for PciSerialBusSubClass {
}
}
/// Mass Storage Sub Classes
#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum PciMassStorageSubclass {
SCSIStorage = 0x00,
IDEInterface = 0x01,
FloppyController = 0x02,
IPIController = 0x03,
RAIDController = 0x04,
ATAController = 0x05,
SATAController = 0x06,
SerialSCSIController = 0x07,
NVMController = 0x08,
MassStorage = 0x80,
}
impl PciSubclass for PciMassStorageSubclass {
fn get_register_value(&self) -> u8 {
*self as u8
}
}
/// Network Controller Sub Classes
#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum PciNetworkControllerSubclass {
EthernetController = 0x00,
TokenRingController = 0x01,
FDDIController = 0x02,
ATMController = 0x03,
ISDNController = 0x04,
WorldFipController = 0x05,
PICMGController = 0x06,
InfinibandController = 0x07,
FabricController = 0x08,
NetworkController = 0x80,
}
impl PciSubclass for PciNetworkControllerSubclass {
fn get_register_value(&self) -> u8 {
*self as u8
}
}
/// A PCI class programming interface. Each combination of `PciClassCode` and
/// `PciSubclass` can specify a set of register-level programming interfaces.
/// This trait is implemented by each programming interface.

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@ -17,8 +17,8 @@ mod root;
pub use self::configuration::{
PciBarConfiguration, PciBarPrefetchable, PciBarRegionType, PciCapability, PciCapabilityID,
PciClassCode, PciConfiguration, PciHeaderType, PciProgrammingInterface, PciSerialBusSubClass,
PciSubclass,
PciClassCode, PciConfiguration, PciHeaderType, PciMassStorageSubclass,
PciNetworkControllerSubclass, PciProgrammingInterface, PciSerialBusSubClass, PciSubclass,
};
pub use self::device::Error as PciDeviceError;
pub use self::device::{InterruptDelivery, InterruptParameters, PciDevice};