From 0e6e539d9b59f233f95b45b570963e23312153b4 Mon Sep 17 00:00:00 2001 From: Jianyong Wu Date: Tue, 8 Nov 2022 14:26:47 +0800 Subject: [PATCH] AArch64/fdt: fix PMU irqflag calculation Currently, CPU mask involved into PMU irqflag caculation which is used for Gicv2. It limits the CPU number up to 31. For Gicv3+, CPU mask is no longer needed. More info see [1]. Signed-off-by: Jianyong Wu [1] https://lore.kernel.org/all/165668798833.3744902.12084627427900181326.b4-ty@kernel.org/t/ --- arch/src/aarch64/fdt.rs | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/src/aarch64/fdt.rs b/arch/src/aarch64/fdt.rs index 3832c5a4a..4bc9c5709 100644 --- a/arch/src/aarch64/fdt.rs +++ b/arch/src/aarch64/fdt.rs @@ -51,8 +51,6 @@ const SIZE_CELLS: u32 = 0x2; // Look for "The 1st cell..." const GIC_FDT_IRQ_TYPE_SPI: u32 = 0; const GIC_FDT_IRQ_TYPE_PPI: u32 = 1; -const GIC_FDT_IRQ_PPI_CPU_SHIFT: u32 = 8; -const GIC_FDT_IRQ_PPI_CPU_MASK: u32 = 0xff << GIC_FDT_IRQ_PPI_CPU_SHIFT; // From https://elixir.bootlin.com/linux/v4.9.62/source/include/dt-bindings/interrupt-controller/irq.h#L17 const IRQ_TYPE_EDGE_RISING: u32 = 1; @@ -121,7 +119,7 @@ pub fn create_fdt FdtWriterResult<()> { - let num_cpus = cpu_nums as u64 as u32; +fn create_pmu_node(fdt: &mut FdtWriter) -> FdtWriterResult<()> { let compatible = "arm,armv8-pmuv3"; - let cpu_mask: u32 = - (((1 << num_cpus) - 1) << GIC_FDT_IRQ_PPI_CPU_SHIFT) & GIC_FDT_IRQ_PPI_CPU_MASK; - let irq = [ - GIC_FDT_IRQ_TYPE_PPI, - AARCH64_PMU_IRQ, - cpu_mask | IRQ_TYPE_LEVEL_HI, - ]; + let irq = [GIC_FDT_IRQ_TYPE_PPI, AARCH64_PMU_IRQ, IRQ_TYPE_LEVEL_HI]; let pmu_node = fdt.begin_node("pmu")?; fdt.property_string("compatible", compatible)?;