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pci: msi: Fix MSG_CTL update through 32 bits write

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If the MSG_CTL is being written from a 32 bits write access, the offset
won't be 0x2, but 0x0 instead. That's simply because 32 bits access have
to be aligned on each double word.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2019-11-26 14:50:53 -08:00 committed by Samuel Ortiz
parent c81e808e98
commit 1379abb94b
1 changed files with 1 additions and 1 deletions
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2
pci/src/msi.rs
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@ -132,7 +132,7 @@ impl MsiCap {
4 => { 4 => {
let value = LittleEndian::read_u32(data); let value = LittleEndian::read_u32(data);
match offset { match offset {
MSI_MSG_CTL_OFFSET => { 0x0 => {
self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE)) self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
| ((value >> 16) as u16 & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE)) | ((value >> 16) as u16 & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
} }