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aarch64: Fix wrong MPIDR setting

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Fixed wrong MPIDR value setting for VCPUs in FDT.
The wrong setting made only 16 VCPUs can be enabled at most, all other
VCPUs were showing off-line.

The issue was introduced when we were migrating FDT-generating code to
vmm-fdt crate.

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
This commit is contained in:
Michael Zhao 2021-06-16 15:31:55 +08:00 committed by Sebastien Boeuf
parent 3c0f06c09c
commit 14c0e8424b
1 changed files with 4 additions and 2 deletions
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6
arch/src/aarch64/fdt.rs
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@ -130,7 +130,7 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult<
fdt.property_u32("#size-cells", 0x0)?;
let num_cpus = vcpu_mpidr.len();
for cpu_id in 0..num_cpus {
for (cpu_id, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) {
let cpu_name = format!("cpu@{:x}", cpu_id);
let cpu_node = fdt.begin_node(&cpu_name)?;
fdt.property_string("device_type", "cpu")?;
@ -139,7 +139,9 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult<
// This is required on armv8 64-bit. See aforementioned documentation.
fdt.property_string("enable-method", "psci")?;
}
fdt.property_u32("reg", cpu_id as u32)?;
// Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register.
// See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html.
fdt.property_u32("reg", (mpidr & 0x7FFFFF) as u32)?;
fdt.end_node(cpu_node)?;
}
fdt.end_node(cpus_node)?;