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aarch64: Fix wrong MPIDR setting
Fixed wrong MPIDR value setting for VCPUs in FDT. The wrong setting made only 16 VCPUs can be enabled at most, all other VCPUs were showing off-line. The issue was introduced when we were migrating FDT-generating code to vmm-fdt crate. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
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@ -130,7 +130,7 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult<
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fdt.property_u32("#size-cells", 0x0)?;
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fdt.property_u32("#size-cells", 0x0)?;
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let num_cpus = vcpu_mpidr.len();
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let num_cpus = vcpu_mpidr.len();
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for cpu_id in 0..num_cpus {
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for (cpu_id, mpidr) in vcpu_mpidr.iter().enumerate().take(num_cpus) {
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let cpu_name = format!("cpu@{:x}", cpu_id);
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let cpu_name = format!("cpu@{:x}", cpu_id);
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let cpu_node = fdt.begin_node(&cpu_name)?;
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let cpu_node = fdt.begin_node(&cpu_name)?;
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fdt.property_string("device_type", "cpu")?;
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fdt.property_string("device_type", "cpu")?;
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@ -139,7 +139,9 @@ fn create_cpu_nodes(fdt: &mut FdtWriter, vcpu_mpidr: &[u64]) -> FdtWriterResult<
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// This is required on armv8 64-bit. See aforementioned documentation.
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// This is required on armv8 64-bit. See aforementioned documentation.
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fdt.property_string("enable-method", "psci")?;
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fdt.property_string("enable-method", "psci")?;
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}
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}
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fdt.property_u32("reg", cpu_id as u32)?;
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// Set the field to first 24 bits of the MPIDR - Multiprocessor Affinity Register.
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// See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488c/BABHBJCI.html.
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fdt.property_u32("reg", (mpidr & 0x7FFFFF) as u32)?;
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fdt.end_node(cpu_node)?;
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fdt.end_node(cpu_node)?;
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}
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}
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fdt.end_node(cpus_node)?;
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fdt.end_node(cpus_node)?;
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