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msix: Remove the need for interrupt callback

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Now that MsixConfig has access to the irq_fd descriptors associated with
each vector, it can directly write to it anytime it needs to trigger an
interrupt.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2020-01-09 23:09:39 +01:00 committed by Samuel Ortiz
parent 3fe362e3bd
commit 19aeac40c9
2 changed files with 4 additions and 20 deletions
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19
pci/src/msix.rs
View File

@ -8,8 +8,7 @@ extern crate vm_memory;
use std::sync::Arc; use std::sync::Arc;
use crate::device::InterruptParameters; use crate::{set_kvm_routes, InterruptRoute, PciCapability, PciCapabilityID};
use crate::{set_kvm_routes, InterruptDelivery, InterruptRoute, PciCapability, PciCapabilityID};
use byteorder::{ByteOrder, LittleEndian}; use byteorder::{ByteOrder, LittleEndian};
use kvm_bindings::{kvm_irq_routing_entry, KVM_IRQ_ROUTING_MSI}; use kvm_bindings::{kvm_irq_routing_entry, KVM_IRQ_ROUTING_MSI};
use kvm_ioctls::VmFd; use kvm_ioctls::VmFd;
@ -59,7 +58,6 @@ pub struct MsixConfig {
pub irq_routes: Vec<InterruptRoute>, pub irq_routes: Vec<InterruptRoute>,
vm_fd: Arc<VmFd>, vm_fd: Arc<VmFd>,
gsi_msi_routes: Arc<Mutex<HashMap<u32, kvm_irq_routing_entry>>>, gsi_msi_routes: Arc<Mutex<HashMap<u32, kvm_irq_routing_entry>>>,
interrupt_cb: Option<Arc<InterruptDelivery>>,
masked: bool, masked: bool,
enabled: bool, enabled: bool,
} }
@ -90,16 +88,11 @@ impl MsixConfig {
irq_routes, irq_routes,
vm_fd, vm_fd,
gsi_msi_routes, gsi_msi_routes,
interrupt_cb: None,
masked: false, masked: false,
enabled: false, enabled: false,
} }
} }
pub fn register_interrupt_cb(&mut self, cb: Arc<InterruptDelivery>) {
self.interrupt_cb = Some(cb);
}
pub fn masked(&self) -> bool { pub fn masked(&self) -> bool {
self.masked self.masked
} }
@ -366,13 +359,9 @@ impl MsixConfig {
fn inject_msix_and_clear_pba(&mut self, vector: usize) { fn inject_msix_and_clear_pba(&mut self, vector: usize) {
// Inject the MSI message // Inject the MSI message
if let Some(cb) = &self.interrupt_cb { match self.irq_routes[vector].irq_fd.write(1) {
match (cb)(InterruptParameters { Ok(_) => debug!("MSI-X injected on vector control flip"),
msix: Some(&self.table_entries[vector]), Err(e) => error!("failed to inject MSI-X: {}", e),
}) {
Ok(_) => debug!("MSI-X injected on vector control flip"),
Err(e) => error!("failed to inject MSI-X: {}", e),
};
} }
// Clear the bit from PBA // Clear the bit from PBA

5
vm-virtio/src/transport/pci_device.rs
View File

@ -498,11 +498,6 @@ impl PciDevice for VirtioPciDevice {
fn assign_msix(&mut self, msi_cb: Arc<InterruptDelivery>) { fn assign_msix(&mut self, msi_cb: Arc<InterruptDelivery>) {
if let Some(msix_config) = &self.msix_config { if let Some(msix_config) = &self.msix_config {
msix_config
.lock()
.unwrap()
.register_interrupt_cb(msi_cb.clone());
let msix_config_clone = msix_config.clone(); let msix_config_clone = msix_config.clone();
let common_config_msi_vector = self.common_config.msix_config.clone(); let common_config_msi_vector = self.common_config.msix_config.clone();