hypervisor: x86: Add an InstructionHandler interface

And an InstructionMap helper structure to map x86 mnemonic codes
to instruction handlers.

Any instruction emulation implementation should then boil down with
implementing InstructionHandler for any supported mnemonic.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

hypervisor/src/arch/x86/emulator/instructions/mod.rs

@@ -0,0 +1,49 @@
+//
+// Copyright © 2020 Intel Corporation
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+
+extern crate iced_x86;
+
+use crate::arch::emulator::{EmulationError, PlatformEmulator};
+use crate::arch::x86::emulator::CpuStateManager;
+use crate::arch::x86::Exception;
+use iced_x86::*;
+use std::collections::HashMap;
+use std::sync::{Arc, Mutex};
+
+pub trait InstructionHandler<T: CpuStateManager> {
+    fn emulate(
+        &self,
+        insn: &Instruction,
+        state: &mut T,
+        platform: Arc<Mutex<dyn PlatformEmulator<CpuState = T>>>,
+    ) -> Result<(), EmulationError<Exception>>;
+}
+
+pub struct InstructionMap<T: CpuStateManager> {
+    pub instructions: HashMap<Code, Box<Box<dyn InstructionHandler<T> + Sync + Send>>>,
+}
+
+impl<T: CpuStateManager> InstructionMap<T> {
+    pub fn new() -> InstructionMap<T> {
+        InstructionMap {
+            instructions: HashMap::new(),
+        }
+    }
+
+    pub fn add_insn(
+        &mut self,
+        insn: Code,
+        insn_handler: Box<dyn InstructionHandler<T> + Sync + Send>,
+    ) {
+        self.instructions.insert(insn, Box::new(insn_handler));
+    }
+}
+
+impl<T: CpuStateManager> Default for InstructionMap<T> {
+    fn default() -> Self {
+        Self::new()
+    }
+}

hypervisor/src/arch/x86/emulator/mod.rs

@@ -10,6 +10,8 @@ use crate::arch::emulator::PlatformError;
 use crate::x86_64::{SegmentRegister, SpecialRegisters, StandardRegisters};
 use iced_x86::*;
 
+mod instructions;
+
 /// CpuStateManager manages an x86 CPU state.
 ///
 /// Instruction emulation handlers get a mutable reference to

hypervisor/src/arch/x86/mod.rs

@@ -38,3 +38,28 @@ pub const MTRR_MEM_TYPE_WB: u64 = 0x6;
 
 // IOAPIC pins
 pub const NUM_IOAPIC_PINS: usize = 24;
+
+// X86 Exceptions
+#[allow(dead_code)]
+#[derive(Clone, Debug)]
+pub enum Exception {
+    DE = 1,  // Divide Error
+    DB = 2,  // Debug Exception
+    BP = 3,  // Breakpoint
+    OF = 4,  // Overflow
+    BR = 5,  // BOUND Range Exceeded
+    UD = 6,  // Invalid/Undefined Opcode
+    NM = 7,  // No Math Coprocessor
+    DF = 8,  // Double Fault
+    TS = 10, // Invalid TSS
+    NP = 11, // Segment Not Present
+    SS = 12, // Stack Segment Fault
+    GP = 13, // General Protection
+    PF = 14, // Page Fault
+    MF = 16, // Math Fault
+    AC = 17, // Alignment Check
+    MC = 18, // Machine Check
+    XM = 19, // SIMD Floating-Point Exception
+    VE = 20, // Virtualization Exception
+    CP = 21, // Control Protection Exception
+}