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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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pci: vfio: Move allocate_bar & free_bars to VfioCommon
This logic can then be shared with the vfio-user implementation. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
Sebastien Boeuf
parent
d27ea34a2d
commit
22275c3462
371
pci/src/vfio.rs
371
pci/src/vfio.rs
@ -306,6 +306,196 @@ struct VfioCommon {
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interrupt: Interrupt,
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}
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impl VfioCommon {
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fn allocate_bars(
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&mut self,
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allocator: &mut SystemAllocator,
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vfio_pci_config: &dyn VfioPciConfig,
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) -> std::result::Result<Vec<(GuestAddress, GuestUsize, PciBarRegionType)>, PciDeviceError>
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{
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let mut ranges = Vec::new();
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let mut bar_id = VFIO_PCI_BAR0_REGION_INDEX as u32;
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// Going through all regular regions to compute the BAR size.
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// We're not saving the BAR address to restore it, because we
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// are going to allocate a guest address for each BAR and write
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// that new address back.
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while bar_id < VFIO_PCI_CONFIG_REGION_INDEX {
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let region_size: u64;
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let bar_addr: GuestAddress;
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let bar_offset = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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(PCI_ROM_EXP_BAR_INDEX * 4) as u32
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} else {
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PCI_CONFIG_BAR_OFFSET + bar_id * 4
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};
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// First read flags
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let flags = vfio_pci_config.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(flags & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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} else {
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false
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};
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// Is this a 64-bit BAR?
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let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(
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flags & PCI_CONFIG_MEMORY_BAR_64BIT,
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PCI_CONFIG_MEMORY_BAR_64BIT
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)
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} else {
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false
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};
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// By default, the region type is 32 bits memory BAR.
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let mut region_type = PciBarRegionType::Memory32BitRegion;
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// To get size write all 1s
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vfio_pci_config.write_config_dword(bar_offset, 0xffff_ffff);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = vfio_pci_config.read_config_dword(bar_offset);
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if io_bar {
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#[cfg(target_arch = "x86_64")]
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{
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// IO BAR
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region_type = PciBarRegionType::IoRegion;
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// Mask flag bits (lowest 2 for I/O bars)
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lower &= !0b11;
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// BAR is not enabled
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert bits and add 1 to calculate size
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region_size = (!lower + 1) as u64;
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// The address needs to be 4 bytes aligned.
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bar_addr = allocator
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.allocate_io_addresses(None, region_size, Some(0x4))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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#[cfg(target_arch = "aarch64")]
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unimplemented!()
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} else if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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vfio_pci_config.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = vfio_pci_config.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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// Mask out flag bits (lowest 4 for memory bars)
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combined_size &= !0b1111;
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// BAR is not enabled
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if combined_size == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!combined_size + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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} else {
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// Mask out flag bits (lowest 4 for memory bars)
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lower &= !0b1111;
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!lower + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_hole_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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let reg_idx = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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PCI_ROM_EXP_BAR_INDEX
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} else {
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bar_id as usize
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};
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// We can now build our BAR configuration block.
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let config = PciBarConfiguration::default()
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.set_register_index(reg_idx)
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.set_address(bar_addr.raw_value())
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.set_size(region_size)
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.set_region_type(region_type);
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if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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self.configuration
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.add_pci_rom_bar(&config, flags & 0x1)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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} else {
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self.configuration
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.add_pci_bar(&config)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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}
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ranges.push((bar_addr, region_size, region_type));
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self.mmio_regions.push(MmioRegion {
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start: bar_addr,
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length: region_size,
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type_: region_type,
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index: bar_id as u32,
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mem_slot: None,
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host_addr: None,
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mmap_size: None,
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});
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bar_id += 1;
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if is_64bit_bar {
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bar_id += 1;
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}
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}
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Ok(ranges)
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}
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fn free_bars(
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&mut self,
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allocator: &mut SystemAllocator,
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) -> std::result::Result<(), PciDeviceError> {
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for region in self.mmio_regions.iter() {
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match region.type_ {
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PciBarRegionType::IoRegion => {
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#[cfg(target_arch = "x86_64")]
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allocator.free_io_addresses(region.start, region.length);
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#[cfg(target_arch = "aarch64")]
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error!("I/O region is not supported");
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}
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PciBarRegionType::Memory32BitRegion => {
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allocator.free_mmio_hole_addresses(region.start, region.length);
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}
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PciBarRegionType::Memory64BitRegion => {
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allocator.free_mmio_addresses(region.start, region.length);
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}
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}
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}
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Ok(())
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}
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}
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/// VfioPciDevice represents a VFIO PCI device.
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/// This structure implements the BusDevice and PciDevice traits.
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///
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@ -828,190 +1018,15 @@ impl PciDevice for VfioPciDevice {
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allocator: &mut SystemAllocator,
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) -> std::result::Result<Vec<(GuestAddress, GuestUsize, PciBarRegionType)>, PciDeviceError>
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{
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let mut ranges = Vec::new();
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let mut bar_id = VFIO_PCI_BAR0_REGION_INDEX as u32;
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// Going through all regular regions to compute the BAR size.
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// We're not saving the BAR address to restore it, because we
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// are going to allocate a guest address for each BAR and write
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// that new address back.
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while bar_id < VFIO_PCI_CONFIG_REGION_INDEX {
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let region_size: u64;
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let bar_addr: GuestAddress;
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let bar_offset = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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(PCI_ROM_EXP_BAR_INDEX * 4) as u32
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} else {
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PCI_CONFIG_BAR_OFFSET + bar_id * 4
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};
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// First read flags
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let flags = self.vfio_pci_configuration.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(flags & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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} else {
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false
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};
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// Is this a 64-bit BAR?
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let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(
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flags & PCI_CONFIG_MEMORY_BAR_64BIT,
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PCI_CONFIG_MEMORY_BAR_64BIT
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)
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} else {
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false
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};
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// By default, the region type is 32 bits memory BAR.
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let mut region_type = PciBarRegionType::Memory32BitRegion;
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// To get size write all 1s
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self.vfio_pci_configuration
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.write_config_dword(bar_offset, 0xffff_ffff);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = self.vfio_pci_configuration.read_config_dword(bar_offset);
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if io_bar {
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#[cfg(target_arch = "x86_64")]
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{
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// IO BAR
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region_type = PciBarRegionType::IoRegion;
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// Mask flag bits (lowest 2 for I/O bars)
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lower &= !0b11;
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// BAR is not enabled
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert bits and add 1 to calculate size
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region_size = (!lower + 1) as u64;
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// The address needs to be 4 bytes aligned.
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bar_addr = allocator
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.allocate_io_addresses(None, region_size, Some(0x4))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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#[cfg(target_arch = "aarch64")]
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unimplemented!()
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} else if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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self.vfio_pci_configuration
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.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = self.vfio_pci_configuration.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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// Mask out flag bits (lowest 4 for memory bars)
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combined_size &= !0b1111;
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// BAR is not enabled
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if combined_size == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!combined_size + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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} else {
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// Mask out flag bits (lowest 4 for memory bars)
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lower &= !0b1111;
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!lower + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_hole_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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let reg_idx = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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PCI_ROM_EXP_BAR_INDEX
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} else {
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bar_id as usize
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};
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// We can now build our BAR configuration block.
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let config = PciBarConfiguration::default()
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.set_register_index(reg_idx)
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.set_address(bar_addr.raw_value())
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.set_size(region_size)
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.set_region_type(region_type);
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if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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self.common
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.configuration
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.add_pci_rom_bar(&config, flags & 0x1)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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} else {
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self.common
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.configuration
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.add_pci_bar(&config)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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}
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ranges.push((bar_addr, region_size, region_type));
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self.common.mmio_regions.push(MmioRegion {
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start: bar_addr,
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length: region_size,
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type_: region_type,
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index: bar_id as u32,
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mem_slot: None,
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host_addr: None,
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mmap_size: None,
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});
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bar_id += 1;
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if is_64bit_bar {
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bar_id += 1;
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}
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}
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Ok(ranges)
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self.common
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.allocate_bars(allocator, &self.vfio_pci_configuration)
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}
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fn free_bars(
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&mut self,
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allocator: &mut SystemAllocator,
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) -> std::result::Result<(), PciDeviceError> {
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for region in self.common.mmio_regions.iter() {
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match region.type_ {
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PciBarRegionType::IoRegion => {
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#[cfg(target_arch = "x86_64")]
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allocator.free_io_addresses(region.start, region.length);
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#[cfg(target_arch = "aarch64")]
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error!("I/O region is not supported");
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}
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PciBarRegionType::Memory32BitRegion => {
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allocator.free_mmio_hole_addresses(region.start, region.length);
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}
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PciBarRegionType::Memory64BitRegion => {
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allocator.free_mmio_addresses(region.start, region.length);
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}
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}
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}
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Ok(())
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self.common.free_bars(allocator)
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}
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fn write_config_register(
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