From 2501426e47b3af9923a70d5e29cc3a1bb7253731 Mon Sep 17 00:00:00 2001
From: Jinank Jain <jinankjain@microsoft.com>
Date: Thu, 21 Mar 2024 09:31:05 +0530
Subject: [PATCH] hypervisor: mshv: Restrict APIC EOI message to x86

APIC controller is only available on x86 machine. ARM uses a different
interrupt controller so those exit messages won't happen for ARM guests.

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
---
 hypervisor/src/mshv/mod.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hypervisor/src/mshv/mod.rs b/hypervisor/src/mshv/mod.rs
index 99b2cddc7..8431c9e30 100644
--- a/hypervisor/src/mshv/mod.rs
+++ b/hypervisor/src/mshv/mod.rs
@@ -706,6 +706,7 @@ impl cpu::Vcpu for MshvVcpu {
                     debug!("Exception Info {:?}", { info.exception_vector });
                     Ok(cpu::VmExit::Ignore)
                 }
+                #[cfg(target_arch = "x86_64")]
                 hv_message_type_HVMSG_X64_APIC_EOI => {
                     let info = x.to_apic_eoi_info().unwrap();
                     // The kernel should dispatch the EOI to the correct thread.