From 29878956bd71ff30b92d09c8b982ba7a6f534d63 Mon Sep 17 00:00:00 2001
From: Samuel Ortiz <sameo@linux.intel.com>
Date: Wed, 3 Jul 2019 19:15:50 +0200
Subject: [PATCH] pci: Implement the From trait for the PciCapabilityID
 structure

This will be needed by the VFIO crate for managing MSI capabilities.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
---
 pci/src/configuration.rs | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/pci/src/configuration.rs b/pci/src/configuration.rs
index ef85550ea..276accdbe 100755
--- a/pci/src/configuration.rs
+++ b/pci/src/configuration.rs
@@ -178,7 +178,10 @@ pub trait PciProgrammingInterface {
 }
 
 /// Types of PCI capabilities.
-#[derive(PartialEq)]
+#[derive(PartialEq, Copy, Clone)]
+#[allow(dead_code)]
+#[allow(non_camel_case_types)]
+#[repr(C)]
 pub enum PciCapabilityID {
     ListID = 0,
     PowerManagement = 0x01,
@@ -203,6 +206,35 @@ pub enum PciCapabilityID {
     PCIEnhancedAllocation = 0x14,
 }
 
+impl From<u8> for PciCapabilityID {
+    fn from(c: u8) -> Self {
+        match c {
+            0 => PciCapabilityID::ListID,
+            0x01 => PciCapabilityID::PowerManagement,
+            0x02 => PciCapabilityID::AcceleratedGraphicsPort,
+            0x03 => PciCapabilityID::VitalProductData,
+            0x04 => PciCapabilityID::SlotIdentification,
+            0x05 => PciCapabilityID::MessageSignalledInterrupts,
+            0x06 => PciCapabilityID::CompactPCIHotSwap,
+            0x07 => PciCapabilityID::PCIX,
+            0x08 => PciCapabilityID::HyperTransport,
+            0x09 => PciCapabilityID::VendorSpecific,
+            0x0A => PciCapabilityID::Debugport,
+            0x0B => PciCapabilityID::CompactPCICentralResourceControl,
+            0x0C => PciCapabilityID::PCIStandardHotPlugController,
+            0x0D => PciCapabilityID::BridgeSubsystemVendorDeviceID,
+            0x0E => PciCapabilityID::AGPTargetPCIPCIbridge,
+            0x0F => PciCapabilityID::SecureDevice,
+            0x10 => PciCapabilityID::PCIExpress,
+            0x11 => PciCapabilityID::MSIX,
+            0x12 => PciCapabilityID::SATADataIndexConf,
+            0x13 => PciCapabilityID::PCIAdvancedFeatures,
+            0x14 => PciCapabilityID::PCIEnhancedAllocation,
+            _ => PciCapabilityID::ListID,
+        }
+    }
+}
+
 /// A PCI capability list. Devices can optionally specify capabilities in their configuration space.
 pub trait PciCapability {
     fn bytes(&self) -> &[u8];