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hypervisor: mshv: explicitly skip a few IO ports
OVMF would use string IO on those ports. String IO has not been implemented, so that leads to panics. Skip them explicitly in MSHV. Leave a long-ish comment in code to explain the situation. We should properly implement string IO once it becomes feasible / necessary. Signed-off-by: Wei Liu <liuwe@microsoft.com>
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@ -322,17 +322,52 @@ impl cpu::Vcpu for MshvVcpu {
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hv_message_type_HVMSG_X64_IO_PORT_INTERCEPT => {
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let info = x.to_ioport_info().unwrap();
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let access_info = info.access_info;
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let len = unsafe { access_info.__bindgen_anon_1.access_size() } as usize;
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let is_write = info.header.intercept_access_type == 1;
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let port = info.port_number;
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let mut data: [u8; 4] = [0; 4];
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let mut ret_rax = info.rax;
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/*
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* XXX: Ignore QEMU fw_cfg (0x5xx) and debug console (0x402) ports.
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*
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* Cloud Hypervisor doesn't support fw_cfg at the moment. It does support 0x402
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* under the "fwdebug" feature flag. But that feature is not enabled by default
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* and is considered legacy.
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*
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* OVMF unconditionally pokes these IO ports with string IO.
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*
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* Instead of trying to implement string IO support now which does not do much
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* now, skip those ports explicitly to avoid panicking.
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*
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* Proper string IO support can be added once we gain the ability to translate
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* guest virtual addresses to guest physical addresses on MSHV.
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*/
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match port {
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0x402 | 0x510 | 0x511 | 0x514 => {
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let insn_len = info.header.instruction_length() as u64;
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/* Advance RIP and update RAX */
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let arr_reg_name_value = [
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(
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hv_register_name::HV_X64_REGISTER_RIP,
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info.header.rip + insn_len,
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),
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(hv_register_name::HV_X64_REGISTER_RAX, ret_rax),
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];
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set_registers_64!(self.fd, arr_reg_name_value)
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.map_err(|e| cpu::HypervisorCpuError::SetRegister(e.into()))?;
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return Ok(cpu::VmExit::Ignore);
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}
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_ => {}
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}
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if unsafe { access_info.__bindgen_anon_1.string_op() } == 1 {
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panic!("String IN/OUT not supported");
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}
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if unsafe { access_info.__bindgen_anon_1.rep_prefix() } == 1 {
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panic!("Rep IN/OUT not supported");
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}
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let len = unsafe { access_info.__bindgen_anon_1.access_size() } as usize;
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let is_write = info.header.intercept_access_type == 1;
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let port = info.port_number;
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let mut data: [u8; 4] = [0; 4];
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let mut ret_rax = info.rax;
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if is_write {
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let data = (info.rax as u32).to_le_bytes();
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