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vm-virtio: Fix broken write_base_regs() unit test
The following commit broke this unit test: """ vmm: Convert virtio devices to Arc<Mutex<T>> Migratable devices can be virtio or legacy devices. In any case, they can potentially be tracked through one of the IO bus as an Arc<Mutex<dyn BusDevice>>. In order for the DeviceManager to also keep track of such devices as Migratable trait objects, they must be shared as mutable atomic references, i.e. Arc<Mutex<T>>. That forces all Migratable objects to be tracked as Arc<Mutex<dyn Migratable>>. Virtio devices are typically migratable, and thus for them to be referenced by the DeviceManager, they now should be built as Arc<Mutex<VirtioDevice>>. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com> """ Signed-off-by: Rob Bradford <robert.bradford@intel.com>
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@ -302,41 +302,41 @@ mod tests {
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msix_config: Arc::new(AtomicU16::new(0)),
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msix_config: Arc::new(AtomicU16::new(0)),
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};
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};
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let dev = &mut DummyDevice(0) as &mut dyn VirtioDevice;
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let dev = Arc::new(Mutex::new(DummyDevice(0)));
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let mut queues = Vec::new();
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let mut queues = Vec::new();
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// Can set all bits of driver_status.
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// Can set all bits of driver_status.
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regs.write(0x14, &[0x55], &mut queues, dev);
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regs.write(0x14, &[0x55], &mut queues, dev.clone());
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let mut read_back = vec![0x00];
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let mut read_back = vec![0x00];
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regs.read(0x14, &mut read_back, &mut queues, dev);
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regs.read(0x14, &mut read_back, &mut queues, dev.clone());
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assert_eq!(read_back[0], 0x55);
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assert_eq!(read_back[0], 0x55);
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// The config generation register is read only.
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// The config generation register is read only.
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regs.write(0x15, &[0xaa], &mut queues, dev);
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regs.write(0x15, &[0xaa], &mut queues, dev.clone());
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let mut read_back = vec![0x00];
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let mut read_back = vec![0x00];
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regs.read(0x15, &mut read_back, &mut queues, dev);
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regs.read(0x15, &mut read_back, &mut queues, dev.clone());
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assert_eq!(read_back[0], 0x55);
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assert_eq!(read_back[0], 0x55);
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// Device features is read-only and passed through from the device.
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// Device features is read-only and passed through from the device.
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regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev);
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regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev.clone());
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let mut read_back = vec![0, 0, 0, 0];
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x04, &mut read_back, &mut queues, dev);
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regs.read(0x04, &mut read_back, &mut queues, dev.clone());
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assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
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assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
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// Feature select registers are read/write.
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// Feature select registers are read/write.
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regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev);
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regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev.clone());
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let mut read_back = vec![0, 0, 0, 0];
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x00, &mut read_back, &mut queues, dev);
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regs.read(0x00, &mut read_back, &mut queues, dev.clone());
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev);
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regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev.clone());
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let mut read_back = vec![0, 0, 0, 0];
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x08, &mut read_back, &mut queues, dev);
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regs.read(0x08, &mut read_back, &mut queues, dev.clone());
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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// 'queue_select' can be read and written.
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// 'queue_select' can be read and written.
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regs.write(0x16, &[0xaa, 0x55], &mut queues, dev);
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regs.write(0x16, &[0xaa, 0x55], &mut queues, dev.clone());
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let mut read_back = vec![0x00, 0x00];
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let mut read_back = vec![0x00, 0x00];
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regs.read(0x16, &mut read_back, &mut queues, dev);
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regs.read(0x16, &mut read_back, &mut queues, dev.clone());
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assert_eq!(read_back[0], 0xaa);
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assert_eq!(read_back[0], 0xaa);
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assert_eq!(read_back[1], 0x55);
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assert_eq!(read_back[1], 0x55);
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}
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}
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