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vm-virtio: Fix broken write_base_regs() unit test

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The following commit broke this unit test:

"""
vmm: Convert virtio devices to Arc<Mutex<T>>

Migratable devices can be virtio or legacy devices.
In any case, they can potentially be tracked through one of the IO bus
as an Arc<Mutex<dyn BusDevice>>. In order for the DeviceManager to also
keep track of such devices as Migratable trait objects, they must be
shared as mutable atomic references, i.e. Arc<Mutex<T>>. That forces all
Migratable objects to be tracked as Arc<Mutex<dyn Migratable>>.

Virtio devices are typically migratable, and thus for them to be
referenced by the DeviceManager, they now should be built as
Arc<Mutex<VirtioDevice>>.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
"""

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford 2020-01-02 16:27:04 +00:00 committed by Sebastien Boeuf
parent b2589d4f3f
commit 32a39f9b95
1 changed files with 13 additions and 13 deletions
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26
vm-virtio/src/transport/pci_common_config.rs
View File

@ -302,41 +302,41 @@ mod tests {
msix_config: Arc::new(AtomicU16::new(0)),
};
let dev = &mut DummyDevice(0) as &mut dyn VirtioDevice;
let dev = Arc::new(Mutex::new(DummyDevice(0)));
let mut queues = Vec::new();
// Can set all bits of driver_status.
regs.write(0x14, &[0x55], &mut queues, dev);
regs.write(0x14, &[0x55], &mut queues, dev.clone());
let mut read_back = vec![0x00];
regs.read(0x14, &mut read_back, &mut queues, dev);
regs.read(0x14, &mut read_back, &mut queues, dev.clone());
assert_eq!(read_back[0], 0x55);
// The config generation register is read only.
regs.write(0x15, &[0xaa], &mut queues, dev);
regs.write(0x15, &[0xaa], &mut queues, dev.clone());
let mut read_back = vec![0x00];
regs.read(0x15, &mut read_back, &mut queues, dev);
regs.read(0x15, &mut read_back, &mut queues, dev.clone());
assert_eq!(read_back[0], 0x55);
// Device features is read-only and passed through from the device.
regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev);
regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev.clone());
let mut read_back = vec![0, 0, 0, 0];
regs.read(0x04, &mut read_back, &mut queues, dev);
regs.read(0x04, &mut read_back, &mut queues, dev.clone());
assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
// Feature select registers are read/write.
regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev);
regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev.clone());
let mut read_back = vec![0, 0, 0, 0];
regs.read(0x00, &mut read_back, &mut queues, dev);
regs.read(0x00, &mut read_back, &mut queues, dev.clone());
assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev);
regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev.clone());
let mut read_back = vec![0, 0, 0, 0];
regs.read(0x08, &mut read_back, &mut queues, dev);
regs.read(0x08, &mut read_back, &mut queues, dev.clone());
assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
// 'queue_select' can be read and written.
regs.write(0x16, &[0xaa, 0x55], &mut queues, dev);
regs.write(0x16, &[0xaa, 0x55], &mut queues, dev.clone());
let mut read_back = vec![0x00, 0x00];
regs.read(0x16, &mut read_back, &mut queues, dev);
regs.read(0x16, &mut read_back, &mut queues, dev.clone());
assert_eq!(read_back[0], 0xaa);
assert_eq!(read_back[1], 0x55);
}