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vfio: pci: Mask multi function device bit
In order to support VFIO for devices supporting multiple functions, we need to mask the multi-function bit (bit 7 from Header Type byte). Otherwise, the guest kernel ends up tryng to enumerate those devices. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
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@ -694,8 +694,6 @@ impl BusDevice for VfioPciDevice {
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// First BAR offset in the PCI config space.
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const PCI_CONFIG_BAR_OFFSET: u32 = 0x10;
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// First BAR register index
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const PCI_CONFIG_BAR0_INDEX: usize = 4;
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// Capability register offset in the PCI config space.
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const PCI_CONFIG_CAPABILITY_OFFSET: u32 = 0x34;
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// IO BAR when first BAR bit is 1.
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@ -708,6 +706,10 @@ const PCI_CONFIG_MEMORY_BAR_64BIT: u32 = 0x4;
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const PCI_CONFIG_REGISTER_SIZE: usize = 4;
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// Number of BARs for a PCI device
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const BAR_NUMS: usize = 6;
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// PCI Header Type register index
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const PCI_HEADER_TYPE_REG_INDEX: usize = 3;
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// First BAR register index
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const PCI_CONFIG_BAR0_INDEX: usize = 4;
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// PCI ROM expansion BAR register index
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const PCI_ROM_EXP_BAR_INDEX: usize = 12;
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// PCI interrupt pin and line register index
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@ -915,8 +917,14 @@ impl PciDevice for VfioPciDevice {
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// mask in case the register being read correspond to the interrupt
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// register, this code makes sure to always expose an Interrupt Pin
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// value of 0, which stands for no interrupt pin support.
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//
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// Since we don't support passing multi-functions devices, we should
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// mask the multi-function bit, bit 7 of the Header Type byte on the
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// register 3.
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let mask = if reg_idx == PCI_INTX_REG_INDEX {
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0xffff_00ff
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} else if reg_idx == PCI_HEADER_TYPE_REG_INDEX {
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0xff7f_ffff
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} else {
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0xffff_ffff
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};
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