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pci: vfio: Restore BARs in a more straightforward way
In case a list of resources is provided to allocate_bars(), it directly means we're restoring some existing BARs. That's why we shouldn't share the codepath that creates BARs from scratch as we don't need to interact with the device to retrieve the information. Whenever resources are provided, we simply iterate over the list of possible BAR indexes and create the BARs if the resource could be found. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf
Bo Chen
parent
11e9f43305
commit
37521ddff7
216
pci/src/vfio.rs
216
pci/src/vfio.rs
@ -373,129 +373,151 @@ impl VfioCommon {
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// are going to allocate a guest address for each BAR and write
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// that new address back.
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while bar_id < VFIO_PCI_CONFIG_REGION_INDEX {
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let region_size: u64;
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let bar_addr: GuestAddress;
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let mut region_size: u64 = 0;
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let mut region_type = PciBarRegionType::Memory32BitRegion;
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let mut flags: u32 = 0;
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let mut restored_bar_addr = None;
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if let Some(resources) = &resources {
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for resource in resources {
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if let Resource::PciBar { index, base, .. } = resource {
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if let Resource::PciBar {
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index,
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base,
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size,
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type_,
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..
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} = resource
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{
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if *index == bar_id as usize {
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restored_bar_addr = Some(GuestAddress(*base));
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region_size = *size;
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region_type = PciBarRegionType::from(*type_);
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break;
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}
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}
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}
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}
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let bar_offset = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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(PCI_ROM_EXP_BAR_INDEX * 4) as u32
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} else {
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PCI_CONFIG_BAR_OFFSET + bar_id * 4
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};
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// First read flags
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let flags = vfio_wrapper.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(flags & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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} else {
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false
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};
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// Is this a 64-bit BAR?
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let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(
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flags & PCI_CONFIG_MEMORY_BAR_64BIT,
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PCI_CONFIG_MEMORY_BAR_64BIT
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)
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} else {
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false
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};
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// By default, the region type is 32 bits memory BAR.
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let mut region_type = PciBarRegionType::Memory32BitRegion;
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// To get size write all 1s
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vfio_wrapper.write_config_dword(bar_offset, 0xffff_ffff);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = vfio_wrapper.read_config_dword(bar_offset);
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if io_bar {
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// Mask flag bits (lowest 2 for I/O bars)
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lower &= !0b11;
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// BAR is not enabled
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if lower == 0 {
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if restored_bar_addr.is_none() {
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bar_id += 1;
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continue;
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}
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} else {
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let bar_offset = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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(PCI_ROM_EXP_BAR_INDEX * 4) as u32
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} else {
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PCI_CONFIG_BAR_OFFSET + bar_id * 4
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};
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// First read flags
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flags = vfio_wrapper.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(flags & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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} else {
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false
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};
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// Is this a 64-bit BAR?
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let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(
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flags & PCI_CONFIG_MEMORY_BAR_64BIT,
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PCI_CONFIG_MEMORY_BAR_64BIT
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)
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} else {
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false
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};
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// To get size write all 1s
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vfio_wrapper.write_config_dword(bar_offset, 0xffff_ffff);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = vfio_wrapper.read_config_dword(bar_offset);
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if io_bar {
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// Mask flag bits (lowest 2 for I/O bars)
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lower &= !0b11;
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// BAR is not enabled
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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#[cfg(target_arch = "x86_64")]
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{
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// IO BAR
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region_type = PciBarRegionType::IoRegion;
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// Invert bits and add 1 to calculate size
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region_size = (!lower + 1) as u64;
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} else if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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vfio_wrapper.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = vfio_wrapper.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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// Mask out flag bits (lowest 4 for memory bars)
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combined_size &= !0b1111;
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// BAR is not enabled
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if combined_size == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!combined_size + 1) as u64;
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} else {
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region_type = PciBarRegionType::Memory32BitRegion;
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// Mask out flag bits (lowest 4 for memory bars)
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lower &= !0b1111;
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!lower + 1) as u64;
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}
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}
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let bar_addr = match region_type {
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PciBarRegionType::IoRegion => {
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#[cfg(target_arch = "aarch64")]
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unimplemented!();
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// The address needs to be 4 bytes aligned.
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bar_addr = allocator
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#[cfg(not(target_arch = "aarch64"))]
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allocator
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.lock()
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.unwrap()
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.allocate_io_addresses(restored_bar_addr, region_size, Some(0x4))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?
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}
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#[cfg(target_arch = "aarch64")]
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unimplemented!()
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} else if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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vfio_wrapper.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = vfio_wrapper.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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// Mask out flag bits (lowest 4 for memory bars)
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combined_size &= !0b1111;
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// BAR is not enabled
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if combined_size == 0 {
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bar_id += 1;
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continue;
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PciBarRegionType::Memory32BitRegion => {
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// BAR allocation must be naturally aligned
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allocator
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.lock()
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.unwrap()
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.allocate_mmio_hole_addresses(
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restored_bar_addr,
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region_size,
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Some(region_size),
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)
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?
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}
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// Invert and add 1 to to find size
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region_size = (!combined_size + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = mmio_allocator
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.allocate(restored_bar_addr, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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} else {
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// Mask out flag bits (lowest 4 for memory bars)
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lower &= !0b1111;
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if lower == 0 {
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bar_id += 1;
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continue;
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PciBarRegionType::Memory64BitRegion => {
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// BAR allocation must be naturally aligned
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mmio_allocator
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.allocate(restored_bar_addr, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?
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}
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// Invert and add 1 to to find size
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region_size = (!lower + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.lock()
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.unwrap()
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.allocate_mmio_hole_addresses(restored_bar_addr, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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};
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// We can now build our BAR configuration block.
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let bar = PciBarConfiguration::default()
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@ -527,7 +549,7 @@ impl VfioCommon {
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});
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bar_id += 1;
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if is_64bit_bar {
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if region_type == PciBarRegionType::Memory64BitRegion {
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bar_id += 1;
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}
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}
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