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vfio: Don't expose an Interrupt Pin

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Since our VFIO code does not support pin based interrupt, but only MSI
and MSI-X, it is cleaner to not expose any Interrupt Pin to the guest by
setting its value to 0.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2019-07-24 22:07:50 -07:00 committed by Rob Bradford
parent 2f802880c0
commit 421b896ab7
1 changed files with 14 additions and 0 deletions
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14
vfio/src/vfio_pci.rs
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@ -708,6 +708,8 @@ const PCI_CONFIG_REGISTER_SIZE: usize = 4;
const BAR_NUMS: usize = 6;
// PCI ROM expansion BAR register index
const PCI_ROM_EXP_BAR_INDEX: usize = 12;
// PCI interrupt pin and line register index
const PCI_INTX_REG_INDEX: usize = 15;
impl PciDevice for VfioPciDevice {
fn allocate_bars(
@ -904,9 +906,21 @@ impl PciDevice for VfioPciDevice {
return 0;
}
// Since we don't support INTx (only MSI and MSI-X), we should not
// expose an invalid Interrupt Pin to the guest. By using a specific
// mask in case the register being read correspond to the interrupt
// register, this code makes sure to always expose an Interrupt Pin
// value of 0, which stands for no interrupt pin support.
let mask = if reg_idx == PCI_INTX_REG_INDEX {
0xffff_00ff
} else {
0xffff_ffff
};
// The config register read comes from the VFIO device itself.
self.vfio_pci_configuration
.read_config_dword((reg_idx * 4) as u32)
& mask
}
fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {