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vfio: Don't expose an Interrupt Pin
Since our VFIO code does not support pin based interrupt, but only MSI and MSI-X, it is cleaner to not expose any Interrupt Pin to the guest by setting its value to 0. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
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@ -708,6 +708,8 @@ const PCI_CONFIG_REGISTER_SIZE: usize = 4;
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const BAR_NUMS: usize = 6;
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const BAR_NUMS: usize = 6;
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// PCI ROM expansion BAR register index
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// PCI ROM expansion BAR register index
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const PCI_ROM_EXP_BAR_INDEX: usize = 12;
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const PCI_ROM_EXP_BAR_INDEX: usize = 12;
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// PCI interrupt pin and line register index
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const PCI_INTX_REG_INDEX: usize = 15;
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impl PciDevice for VfioPciDevice {
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impl PciDevice for VfioPciDevice {
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fn allocate_bars(
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fn allocate_bars(
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@ -904,9 +906,21 @@ impl PciDevice for VfioPciDevice {
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return 0;
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return 0;
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}
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}
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// Since we don't support INTx (only MSI and MSI-X), we should not
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// expose an invalid Interrupt Pin to the guest. By using a specific
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// mask in case the register being read correspond to the interrupt
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// register, this code makes sure to always expose an Interrupt Pin
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// value of 0, which stands for no interrupt pin support.
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let mask = if reg_idx == PCI_INTX_REG_INDEX {
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0xffff_00ff
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} else {
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0xffff_ffff
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};
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// The config register read comes from the VFIO device itself.
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// The config register read comes from the VFIO device itself.
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self.vfio_pci_configuration
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self.vfio_pci_configuration
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.read_config_dword((reg_idx * 4) as u32)
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.read_config_dword((reg_idx * 4) as u32)
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& mask
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}
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}
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fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
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fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
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