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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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pci: Move VfioWrapper to VfioCommon
Extend VfioCommon to simplify the overall code, and also in preparation for supporting the restore code path. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf
parent
e6aa792c01
commit
4a99d3dbaf
146
pci/src/vfio.rs
146
pci/src/vfio.rs
@ -236,7 +236,7 @@ pub enum VfioError {
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VfioUser(#[source] vfio_user::Error),
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}
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pub(crate) trait Vfio {
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pub(crate) trait Vfio: Send + Sync {
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fn read_config_byte(&self, offset: u32) -> u8 {
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let mut data: [u8; 1] = [0];
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self.read_config(offset, &mut data);
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@ -357,6 +357,7 @@ pub(crate) struct VfioCommon {
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pub(crate) interrupt: Interrupt,
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pub(crate) msi_interrupt_manager: Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
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pub(crate) legacy_interrupt_group: Option<Arc<dyn InterruptSourceGroup>>,
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pub(crate) vfio_wrapper: Arc<dyn Vfio>,
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}
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impl VfioCommon {
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@ -364,7 +365,6 @@ impl VfioCommon {
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&mut self,
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allocator: &Arc<Mutex<SystemAllocator>>,
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mmio_allocator: &mut AddressAllocator,
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vfio_wrapper: &dyn Vfio,
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resources: Option<Vec<Resource>>,
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) -> Result<Vec<PciBarConfiguration>, PciDeviceError> {
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let mut bars = Vec::new();
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@ -410,7 +410,7 @@ impl VfioCommon {
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};
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// First read flags
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flags = vfio_wrapper.read_config_dword(bar_offset);
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flags = self.vfio_wrapper.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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@ -430,10 +430,11 @@ impl VfioCommon {
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};
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// To get size write all 1s
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vfio_wrapper.write_config_dword(bar_offset, 0xffff_ffff);
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self.vfio_wrapper
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.write_config_dword(bar_offset, 0xffff_ffff);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = vfio_wrapper.read_config_dword(bar_offset);
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let mut lower = self.vfio_wrapper.read_config_dword(bar_offset);
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if io_bar {
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// Mask flag bits (lowest 2 for I/O bars)
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@ -456,8 +457,9 @@ impl VfioCommon {
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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vfio_wrapper.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = vfio_wrapper.read_config_dword(upper_offset);
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self.vfio_wrapper
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.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = self.vfio_wrapper.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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@ -583,12 +585,12 @@ impl VfioCommon {
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Ok(())
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}
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pub(crate) fn parse_msix_capabilities(&mut self, cap: u8, vfio_wrapper: &dyn Vfio) -> MsixCap {
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let msg_ctl = vfio_wrapper.read_config_word((cap + 2).into());
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pub(crate) fn parse_msix_capabilities(&mut self, cap: u8) -> MsixCap {
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let msg_ctl = self.vfio_wrapper.read_config_word((cap + 2).into());
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let table = vfio_wrapper.read_config_dword((cap + 4).into());
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let table = self.vfio_wrapper.read_config_dword((cap + 4).into());
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let pba = vfio_wrapper.read_config_dword((cap + 8).into());
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let pba = self.vfio_wrapper.read_config_dword((cap + 8).into());
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MsixCap {
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msg_ctl,
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@ -620,8 +622,8 @@ impl VfioCommon {
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});
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}
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pub(crate) fn parse_msi_capabilities(&mut self, cap: u8, vfio_wrapper: &dyn Vfio) -> u16 {
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vfio_wrapper.read_config_word((cap + 2).into())
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pub(crate) fn parse_msi_capabilities(&mut self, cap: u8) -> u16 {
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self.vfio_wrapper.read_config_word((cap + 2).into())
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}
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pub(crate) fn initialize_msi(&mut self, msg_ctl: u16, cap_offset: u32) {
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@ -642,29 +644,32 @@ impl VfioCommon {
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});
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}
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pub(crate) fn parse_capabilities(&mut self, vfio_wrapper: &dyn Vfio, bdf: PciBdf) {
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let mut cap_next = vfio_wrapper.read_config_byte(PCI_CONFIG_CAPABILITY_OFFSET);
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pub(crate) fn parse_capabilities(&mut self, bdf: PciBdf) {
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let mut cap_next = self
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.vfio_wrapper
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.read_config_byte(PCI_CONFIG_CAPABILITY_OFFSET);
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while cap_next != 0 {
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let cap_id = vfio_wrapper.read_config_byte(cap_next.into());
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let cap_id = self.vfio_wrapper.read_config_byte(cap_next.into());
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match PciCapabilityId::from(cap_id) {
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PciCapabilityId::MessageSignalledInterrupts => {
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if let Some(irq_info) = vfio_wrapper.get_irq_info(VFIO_PCI_MSI_IRQ_INDEX) {
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if let Some(irq_info) = self.vfio_wrapper.get_irq_info(VFIO_PCI_MSI_IRQ_INDEX) {
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if irq_info.count > 0 {
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// Parse capability only if the VFIO device
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// supports MSI.
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let msg_ctl = self.parse_msi_capabilities(cap_next, vfio_wrapper);
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let msg_ctl = self.parse_msi_capabilities(cap_next);
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self.initialize_msi(msg_ctl, cap_next as u32);
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}
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}
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}
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PciCapabilityId::MsiX => {
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if let Some(irq_info) = vfio_wrapper.get_irq_info(VFIO_PCI_MSIX_IRQ_INDEX) {
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if let Some(irq_info) = self.vfio_wrapper.get_irq_info(VFIO_PCI_MSIX_IRQ_INDEX)
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{
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if irq_info.count > 0 {
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// Parse capability only if the VFIO device
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// supports MSI-X.
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let msix_cap = self.parse_msix_capabilities(cap_next, vfio_wrapper);
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let msix_cap = self.parse_msix_capabilities(cap_next);
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self.initialize_msix(msix_cap, cap_next as u32, bdf);
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}
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}
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@ -672,15 +677,15 @@ impl VfioCommon {
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_ => {}
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};
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cap_next = vfio_wrapper.read_config_byte((cap_next + 1).into());
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cap_next = self.vfio_wrapper.read_config_byte((cap_next + 1).into());
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}
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}
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pub(crate) fn enable_intx(&mut self, wrapper: &dyn Vfio) -> Result<(), VfioPciError> {
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pub(crate) fn enable_intx(&mut self) -> Result<(), VfioPciError> {
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if let Some(intx) = &mut self.interrupt.intx {
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if !intx.enabled {
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if let Some(eventfd) = intx.interrupt_source_group.notifier(0) {
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wrapper
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self.vfio_wrapper
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.enable_irq(VFIO_PCI_INTX_IRQ_INDEX, vec![&eventfd])
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.map_err(VfioPciError::EnableIntx)?;
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@ -694,10 +699,10 @@ impl VfioCommon {
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Ok(())
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}
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pub(crate) fn disable_intx(&mut self, wrapper: &dyn Vfio) {
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pub(crate) fn disable_intx(&mut self) {
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if let Some(intx) = &mut self.interrupt.intx {
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if intx.enabled {
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if let Err(e) = wrapper.disable_irq(VFIO_PCI_INTX_IRQ_INDEX) {
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if let Err(e) = self.vfio_wrapper.disable_irq(VFIO_PCI_INTX_IRQ_INDEX) {
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error!("Could not disable INTx: {}", e);
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} else {
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intx.enabled = false;
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@ -706,7 +711,7 @@ impl VfioCommon {
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}
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}
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pub(crate) fn enable_msi(&self, wrapper: &dyn Vfio) -> Result<(), VfioPciError> {
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pub(crate) fn enable_msi(&self) -> Result<(), VfioPciError> {
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if let Some(msi) = &self.interrupt.msi {
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let mut irq_fds: Vec<EventFd> = Vec::new();
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for i in 0..msi.cfg.num_enabled_vectors() {
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@ -717,7 +722,7 @@ impl VfioCommon {
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}
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}
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wrapper
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self.vfio_wrapper
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.enable_msi(irq_fds.iter().collect())
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.map_err(VfioPciError::EnableMsi)?;
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}
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@ -725,13 +730,13 @@ impl VfioCommon {
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Ok(())
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}
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pub(crate) fn disable_msi(&self, wrapper: &dyn Vfio) {
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if let Err(e) = wrapper.disable_msi() {
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pub(crate) fn disable_msi(&self) {
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if let Err(e) = self.vfio_wrapper.disable_msi() {
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error!("Could not disable MSI: {}", e);
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}
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}
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pub(crate) fn enable_msix(&self, wrapper: &dyn Vfio) -> Result<(), VfioPciError> {
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pub(crate) fn enable_msix(&self) -> Result<(), VfioPciError> {
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if let Some(msix) = &self.interrupt.msix {
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let mut irq_fds: Vec<EventFd> = Vec::new();
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for i in 0..msix.bar.table_entries.len() {
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@ -742,7 +747,7 @@ impl VfioCommon {
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}
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}
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wrapper
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self.vfio_wrapper
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.enable_msix(irq_fds.iter().collect())
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.map_err(VfioPciError::EnableMsix)?;
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}
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@ -750,17 +755,14 @@ impl VfioCommon {
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Ok(())
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}
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pub(crate) fn disable_msix(&self, wrapper: &dyn Vfio) {
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if let Err(e) = wrapper.disable_msix() {
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pub(crate) fn disable_msix(&self) {
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if let Err(e) = self.vfio_wrapper.disable_msix() {
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error!("Could not disable MSI-X: {}", e);
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}
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}
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pub(crate) fn initialize_legacy_interrupt(
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&mut self,
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wrapper: &dyn Vfio,
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) -> Result<(), VfioPciError> {
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if let Some(irq_info) = wrapper.get_irq_info(VFIO_PCI_INTX_IRQ_INDEX) {
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pub(crate) fn initialize_legacy_interrupt(&mut self) -> Result<(), VfioPciError> {
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if let Some(irq_info) = self.vfio_wrapper.get_irq_info(VFIO_PCI_INTX_IRQ_INDEX) {
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if irq_info.count == 0 {
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// A count of 0 means the INTx IRQ is not supported, therefore
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// it shouldn't be initialized.
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@ -774,7 +776,7 @@ impl VfioCommon {
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enabled: false,
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});
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self.enable_intx(wrapper)?;
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self.enable_intx()?;
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}
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Ok(())
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@ -784,18 +786,17 @@ impl VfioCommon {
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&mut self,
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offset: u64,
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data: &[u8],
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wrapper: &dyn Vfio,
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) -> Result<(), VfioPciError> {
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match self.interrupt.update_msi(offset, data) {
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Some(InterruptUpdateAction::EnableMsi) => {
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// Disable INTx before we can enable MSI
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self.disable_intx(wrapper);
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self.enable_msi(wrapper)?;
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self.disable_intx();
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self.enable_msi()?;
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}
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Some(InterruptUpdateAction::DisableMsi) => {
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// Fallback onto INTx when disabling MSI
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self.disable_msi(wrapper);
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self.enable_intx(wrapper)?;
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self.disable_msi();
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self.enable_intx()?;
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}
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_ => {}
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}
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@ -807,18 +808,17 @@ impl VfioCommon {
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&mut self,
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offset: u64,
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data: &[u8],
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wrapper: &dyn Vfio,
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) -> Result<(), VfioPciError> {
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match self.interrupt.update_msix(offset, data) {
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Some(InterruptUpdateAction::EnableMsix) => {
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// Disable INTx before we can enable MSI-X
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self.disable_intx(wrapper);
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self.enable_msix(wrapper)?;
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self.disable_intx();
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self.enable_msix()?;
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}
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Some(InterruptUpdateAction::DisableMsix) => {
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// Fallback onto INTx when disabling MSI-X
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self.disable_msix(wrapper);
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self.enable_intx(wrapper)?;
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self.disable_msix();
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self.enable_intx()?;
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}
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_ => {}
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}
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@ -837,7 +837,7 @@ impl VfioCommon {
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None
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}
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pub(crate) fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8], wrapper: &dyn Vfio) {
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pub(crate) fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
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let addr = base + offset;
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if let Some(region) = self.find_region(addr) {
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let offset = addr - region.start.raw_value();
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@ -845,7 +845,7 @@ impl VfioCommon {
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if self.interrupt.msix_table_accessed(region.index, offset) {
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self.interrupt.msix_read_table(offset, data);
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} else {
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wrapper.region_read(region.index, offset, data);
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self.vfio_wrapper.region_read(region.index, offset, data);
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}
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}
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@ -853,7 +853,7 @@ impl VfioCommon {
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// The guest reading from the BAR potentially means the interrupt has
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// been received and can be acknowledged.
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if self.interrupt.intx_in_use() {
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if let Err(e) = wrapper.unmask_irq(VFIO_PCI_INTX_IRQ_INDEX) {
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if let Err(e) = self.vfio_wrapper.unmask_irq(VFIO_PCI_INTX_IRQ_INDEX) {
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error!("Failed unmasking INTx IRQ: {}", e);
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}
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}
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@ -864,7 +864,6 @@ impl VfioCommon {
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base: u64,
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offset: u64,
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data: &[u8],
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wrapper: &dyn Vfio,
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) -> Option<Arc<Barrier>> {
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let addr = base + offset;
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if let Some(region) = self.find_region(addr) {
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@ -874,7 +873,7 @@ impl VfioCommon {
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if self.interrupt.msix_table_accessed(region.index, offset) {
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self.interrupt.msix_write_table(offset, data);
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} else {
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wrapper.region_write(region.index, offset, data);
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self.vfio_wrapper.region_write(region.index, offset, data);
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}
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}
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@ -882,7 +881,7 @@ impl VfioCommon {
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// The guest writing to the BAR potentially means the interrupt has
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// been received and can be acknowledged.
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if self.interrupt.intx_in_use() {
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if let Err(e) = wrapper.unmask_irq(VFIO_PCI_INTX_IRQ_INDEX) {
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if let Err(e) = self.vfio_wrapper.unmask_irq(VFIO_PCI_INTX_IRQ_INDEX) {
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error!("Failed unmasking INTx IRQ: {}", e);
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}
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}
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@ -895,7 +894,6 @@ impl VfioCommon {
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reg_idx: usize,
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offset: u64,
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data: &[u8],
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wrapper: &dyn Vfio,
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) -> Option<Arc<Barrier>> {
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// When the guest wants to write to a BAR, we trap it into
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// our local configuration space. We're not reprogramming
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@ -921,12 +919,12 @@ impl VfioCommon {
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let cap_offset: u64 = reg - cap_base + offset;
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match cap_id {
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PciCapabilityId::MessageSignalledInterrupts => {
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if let Err(e) = self.update_msi_capabilities(cap_offset, data, wrapper) {
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if let Err(e) = self.update_msi_capabilities(cap_offset, data) {
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error!("Could not update MSI capabilities: {}", e);
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}
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}
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PciCapabilityId::MsiX => {
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if let Err(e) = self.update_msix_capabilities(cap_offset, data, wrapper) {
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if let Err(e) = self.update_msix_capabilities(cap_offset, data) {
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error!("Could not update MSI-X capabilities: {}", e);
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}
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}
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@ -942,12 +940,12 @@ impl VfioCommon {
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// enabling this bit, we first need to enable the MSI interrupts with
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// VFIO through VFIO_DEVICE_SET_IRQS ioctl, and only after we can write
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// to the device region to update the MSI Enable bit.
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wrapper.write_config((reg + offset) as u32, data);
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self.vfio_wrapper.write_config((reg + offset) as u32, data);
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None
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}
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pub(crate) fn read_config_register(&mut self, reg_idx: usize, wrapper: &dyn Vfio) -> u32 {
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pub(crate) fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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// When reading the BARs, we trap it and return what comes
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// from our local configuration space. We want the guest to
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// use that and not the VFIO device BARs as it does not map
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@ -968,7 +966,7 @@ impl VfioCommon {
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};
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// The config register read comes from the VFIO device itself.
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wrapper.read_config_dword((reg_idx * 4) as u32) & mask
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self.vfio_wrapper.read_config_dword((reg_idx * 4) as u32) & mask
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}
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}
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@ -983,7 +981,6 @@ pub struct VfioPciDevice {
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vm: Arc<dyn hypervisor::Vm>,
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device: Arc<VfioDevice>,
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container: Arc<VfioContainer>,
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vfio_wrapper: VfioDeviceWrapper,
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common: VfioCommon,
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iommu_attached: bool,
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}
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@ -1029,17 +1026,17 @@ impl VfioPciDevice {
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},
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msi_interrupt_manager,
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legacy_interrupt_group,
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vfio_wrapper: Arc::new(vfio_wrapper) as Arc<dyn Vfio>,
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};
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|
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common.parse_capabilities(&vfio_wrapper, bdf);
|
||||
common.initialize_legacy_interrupt(&vfio_wrapper)?;
|
||||
common.parse_capabilities(bdf);
|
||||
common.initialize_legacy_interrupt()?;
|
||||
|
||||
let vfio_pci_device = VfioPciDevice {
|
||||
id,
|
||||
vm: vm.clone(),
|
||||
device,
|
||||
container,
|
||||
vfio_wrapper,
|
||||
common,
|
||||
iommu_attached,
|
||||
};
|
||||
@ -1299,18 +1296,18 @@ impl Drop for VfioPciDevice {
|
||||
|
||||
if let Some(msix) = &self.common.interrupt.msix {
|
||||
if msix.bar.enabled() {
|
||||
self.common.disable_msix(&self.vfio_wrapper);
|
||||
self.common.disable_msix();
|
||||
}
|
||||
}
|
||||
|
||||
if let Some(msi) = &self.common.interrupt.msi {
|
||||
if msi.cfg.enabled() {
|
||||
self.common.disable_msi(&self.vfio_wrapper)
|
||||
self.common.disable_msi()
|
||||
}
|
||||
}
|
||||
|
||||
if self.common.interrupt.intx_in_use() {
|
||||
self.common.disable_intx(&self.vfio_wrapper);
|
||||
self.common.disable_intx();
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1352,7 +1349,7 @@ impl PciDevice for VfioPciDevice {
|
||||
resources: Option<Vec<Resource>>,
|
||||
) -> Result<Vec<PciBarConfiguration>, PciDeviceError> {
|
||||
self.common
|
||||
.allocate_bars(allocator, mmio_allocator, &self.vfio_wrapper, resources)
|
||||
.allocate_bars(allocator, mmio_allocator, resources)
|
||||
}
|
||||
|
||||
fn free_bars(
|
||||
@ -1369,13 +1366,11 @@ impl PciDevice for VfioPciDevice {
|
||||
offset: u64,
|
||||
data: &[u8],
|
||||
) -> Option<Arc<Barrier>> {
|
||||
self.common
|
||||
.write_config_register(reg_idx, offset, data, &self.vfio_wrapper)
|
||||
self.common.write_config_register(reg_idx, offset, data)
|
||||
}
|
||||
|
||||
fn read_config_register(&mut self, reg_idx: usize) -> u32 {
|
||||
self.common
|
||||
.read_config_register(reg_idx, &self.vfio_wrapper)
|
||||
self.common.read_config_register(reg_idx)
|
||||
}
|
||||
|
||||
fn detect_bar_reprogramming(
|
||||
@ -1389,12 +1384,11 @@ impl PciDevice for VfioPciDevice {
|
||||
}
|
||||
|
||||
fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
|
||||
self.common.read_bar(base, offset, data, &self.vfio_wrapper)
|
||||
self.common.read_bar(base, offset, data)
|
||||
}
|
||||
|
||||
fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
|
||||
self.common
|
||||
.write_bar(base, offset, data, &self.vfio_wrapper)
|
||||
self.common.write_bar(base, offset, data)
|
||||
}
|
||||
|
||||
fn move_bar(&mut self, old_base: u64, new_base: u64) -> Result<(), io::Error> {
|
||||
|
||||
@ -32,7 +32,6 @@ pub struct VfioUserPciDevice {
|
||||
id: String,
|
||||
vm: Arc<dyn hypervisor::Vm>,
|
||||
client: Arc<Mutex<Client>>,
|
||||
vfio_wrapper: VfioUserClientWrapper,
|
||||
common: VfioCommon,
|
||||
}
|
||||
|
||||
@ -106,18 +105,18 @@ impl VfioUserPciDevice {
|
||||
},
|
||||
msi_interrupt_manager,
|
||||
legacy_interrupt_group,
|
||||
vfio_wrapper: Arc::new(vfio_wrapper) as Arc<dyn Vfio>,
|
||||
};
|
||||
|
||||
common.parse_capabilities(&vfio_wrapper, bdf);
|
||||
common.parse_capabilities(bdf);
|
||||
common
|
||||
.initialize_legacy_interrupt(&vfio_wrapper)
|
||||
.initialize_legacy_interrupt()
|
||||
.map_err(VfioUserPciDeviceError::InitializeLegacyInterrupts)?;
|
||||
|
||||
Ok(Self {
|
||||
id,
|
||||
vm: vm.clone(),
|
||||
client,
|
||||
vfio_wrapper,
|
||||
common,
|
||||
})
|
||||
}
|
||||
@ -399,7 +398,7 @@ impl PciDevice for VfioUserPciDevice {
|
||||
resources: Option<Vec<Resource>>,
|
||||
) -> Result<Vec<PciBarConfiguration>, PciDeviceError> {
|
||||
self.common
|
||||
.allocate_bars(allocator, mmio_allocator, &self.vfio_wrapper, resources)
|
||||
.allocate_bars(allocator, mmio_allocator, resources)
|
||||
}
|
||||
|
||||
fn free_bars(
|
||||
@ -430,22 +429,19 @@ impl PciDevice for VfioUserPciDevice {
|
||||
offset: u64,
|
||||
data: &[u8],
|
||||
) -> Option<Arc<Barrier>> {
|
||||
self.common
|
||||
.write_config_register(reg_idx, offset, data, &self.vfio_wrapper)
|
||||
self.common.write_config_register(reg_idx, offset, data)
|
||||
}
|
||||
|
||||
fn read_config_register(&mut self, reg_idx: usize) -> u32 {
|
||||
self.common
|
||||
.read_config_register(reg_idx, &self.vfio_wrapper)
|
||||
self.common.read_config_register(reg_idx)
|
||||
}
|
||||
|
||||
fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
|
||||
self.common.read_bar(base, offset, data, &self.vfio_wrapper)
|
||||
self.common.read_bar(base, offset, data)
|
||||
}
|
||||
|
||||
fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
|
||||
self.common
|
||||
.write_bar(base, offset, data, &self.vfio_wrapper)
|
||||
self.common.write_bar(base, offset, data)
|
||||
}
|
||||
|
||||
fn move_bar(&mut self, old_base: u64, new_base: u64) -> Result<(), std::io::Error> {
|
||||
@ -502,18 +498,18 @@ impl Drop for VfioUserPciDevice {
|
||||
|
||||
if let Some(msix) = &self.common.interrupt.msix {
|
||||
if msix.bar.enabled() {
|
||||
self.common.disable_msix(&self.vfio_wrapper);
|
||||
self.common.disable_msix();
|
||||
}
|
||||
}
|
||||
|
||||
if let Some(msi) = &self.common.interrupt.msi {
|
||||
if msi.cfg.enabled() {
|
||||
self.common.disable_msi(&self.vfio_wrapper)
|
||||
self.common.disable_msi()
|
||||
}
|
||||
}
|
||||
|
||||
if self.common.interrupt.intx_in_use() {
|
||||
self.common.disable_intx(&self.vfio_wrapper);
|
||||
self.common.disable_intx();
|
||||
}
|
||||
|
||||
if let Err(e) = self.client.lock().unwrap().shutdown() {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user