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pci: handle extended configuration space properly

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This is critical to support extended capabilitiy list.

Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
This commit is contained in:
Qiu Wenbo 2020-02-20 23:55:22 +08:00 committed by Samuel Ortiz
parent f6b9445be7
commit 4cf89d373d
1 changed files with 2 additions and 2 deletions
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4
pci/src/configuration.rs
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@ -9,8 +9,8 @@ use crate::{MsixConfig, PciInterruptPin};
use byteorder::{ByteOrder, LittleEndian};
use std::fmt::{self, Display};
// The number of 32bit registers in the config space, 256 bytes.
const NUM_CONFIGURATION_REGISTERS: usize = 64;
// The number of 32bit registers in the config space, 4096 bytes.
const NUM_CONFIGURATION_REGISTERS: usize = 1024;
const STATUS_REG: usize = 1;
const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000;