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pci: handle extended configuration space properly
This is critical to support extended capabilitiy list. Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
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@ -9,8 +9,8 @@ use crate::{MsixConfig, PciInterruptPin};
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use byteorder::{ByteOrder, LittleEndian};
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use byteorder::{ByteOrder, LittleEndian};
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use std::fmt::{self, Display};
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use std::fmt::{self, Display};
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// The number of 32bit registers in the config space, 256 bytes.
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// The number of 32bit registers in the config space, 4096 bytes.
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const NUM_CONFIGURATION_REGISTERS: usize = 64;
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const NUM_CONFIGURATION_REGISTERS: usize = 1024;
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const STATUS_REG: usize = 1;
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const STATUS_REG: usize = 1;
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const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000;
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const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000;
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