mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-09-28 17:45:44 +00:00
hypervisor: move away from MsrEntries type
It is a flexible array. Switch to vector and slice instead. No functional change intended. Signed-off-by: Wei Liu <liuwe@microsoft.com>
This commit is contained in:
parent
563919fc4a
commit
4d2cc3778f
@ -17,7 +17,7 @@ use crate::arch::x86::{CpuIdEntry, FpuState, LapicState, SpecialRegisters, Stand
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#[cfg(feature = "tdx")]
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#[cfg(feature = "tdx")]
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use crate::kvm::{TdxExitDetails, TdxExitStatus};
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use crate::kvm::{TdxExitDetails, TdxExitStatus};
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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use crate::x86_64::MsrEntries;
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use crate::x86_64::MsrEntry;
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use crate::CpuState;
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use crate::CpuState;
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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use crate::DeviceAttr;
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use crate::DeviceAttr;
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@ -333,12 +333,12 @@ pub trait Vcpu: Send + Sync {
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///
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///
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/// Returns the model-specific registers (MSR) for this vCPU.
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/// Returns the model-specific registers (MSR) for this vCPU.
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///
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///
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fn get_msrs(&self, msrs: &mut MsrEntries) -> Result<usize>;
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fn get_msrs(&self, msrs: &mut Vec<MsrEntry>) -> Result<usize>;
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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///
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///
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/// Setup the model-specific registers (MSR) for this vCPU.
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/// Setup the model-specific registers (MSR) for this vCPU.
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///
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///
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fn set_msrs(&self, msrs: &MsrEntries) -> Result<usize>;
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fn set_msrs(&self, msrs: &[MsrEntry]) -> Result<usize>;
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///
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///
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/// Returns the vcpu's current "multiprocessing state".
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/// Returns the vcpu's current "multiprocessing state".
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///
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///
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@ -442,5 +442,5 @@ pub trait Vcpu: Send + Sync {
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///
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///
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/// Return the list of initial MSR entries for a VCPU
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/// Return the list of initial MSR entries for a VCPU
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///
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///
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fn boot_msr_entries(&self) -> MsrEntries;
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fn boot_msr_entries(&self) -> Vec<MsrEntry>;
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}
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}
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@ -65,7 +65,7 @@ use kvm_bindings::{
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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use x86_64::check_required_kvm_extensions;
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use x86_64::check_required_kvm_extensions;
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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pub use x86_64::{CpuId, ExtendedControlRegisters, MsrEntries, VcpuKvmState, Xsave};
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pub use x86_64::{CpuId, ExtendedControlRegisters, MsrEntries, MsrEntry, VcpuKvmState, Xsave};
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// aarch64 dependencies
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// aarch64 dependencies
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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pub mod aarch64;
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pub mod aarch64;
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@ -309,7 +309,7 @@ struct KvmDirtyLogSlot {
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pub struct KvmVm {
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pub struct KvmVm {
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fd: Arc<VmFd>,
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fd: Arc<VmFd>,
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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msrs: MsrEntries,
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msrs: Vec<MsrEntry>,
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dirty_log_slots: Arc<RwLock<HashMap<u32, KvmDirtyLogSlot>>>,
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dirty_log_slots: Arc<RwLock<HashMap<u32, KvmDirtyLogSlot>>>,
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}
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}
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@ -950,11 +950,15 @@ impl hypervisor::Hypervisor for KvmHypervisor {
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{
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{
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let msr_list = self.get_msr_list()?;
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let msr_list = self.get_msr_list()?;
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let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
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let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
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let mut msrs = MsrEntries::new(num_msrs).unwrap();
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let mut msrs: Vec<MsrEntry> = vec![
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MsrEntry {
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..Default::default()
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};
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num_msrs
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];
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let indices = msr_list.as_slice();
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let indices = msr_list.as_slice();
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let msr_entries = msrs.as_mut_slice();
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for (pos, index) in indices.iter().enumerate() {
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for (pos, index) in indices.iter().enumerate() {
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msr_entries[pos].index = *index;
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msrs[pos].index = *index;
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}
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}
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Ok(Arc::new(KvmVm {
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Ok(Arc::new(KvmVm {
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@ -1049,7 +1053,7 @@ impl hypervisor::Hypervisor for KvmHypervisor {
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pub struct KvmVcpu {
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pub struct KvmVcpu {
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fd: VcpuFd,
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fd: VcpuFd,
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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msrs: MsrEntries,
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msrs: Vec<MsrEntry>,
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vm_ops: Option<Arc<dyn vm::VmOps>>,
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vm_ops: Option<Arc<dyn vm::VmOps>>,
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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hyperv_synic: AtomicBool,
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hyperv_synic: AtomicBool,
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@ -1398,19 +1402,26 @@ impl cpu::Vcpu for KvmVcpu {
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///
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///
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/// Returns the model-specific registers (MSR) for this vCPU.
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/// Returns the model-specific registers (MSR) for this vCPU.
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///
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///
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fn get_msrs(&self, msrs: &mut MsrEntries) -> cpu::Result<usize> {
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fn get_msrs(&self, msrs: &mut Vec<MsrEntry>) -> cpu::Result<usize> {
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self.fd
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let mut kvm_msrs = MsrEntries::from_entries(msrs).unwrap();
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.get_msrs(msrs)
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let succ = self
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.map_err(|e| cpu::HypervisorCpuError::GetMsrEntries(e.into()))
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.fd
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.get_msrs(&mut kvm_msrs)
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.map_err(|e| cpu::HypervisorCpuError::GetMsrEntries(e.into()))?;
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msrs[..succ].copy_from_slice(&kvm_msrs.as_slice()[..succ]);
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Ok(succ)
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}
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}
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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///
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///
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/// Setup the model-specific registers (MSR) for this vCPU.
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/// Setup the model-specific registers (MSR) for this vCPU.
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/// Returns the number of MSR entries actually written.
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/// Returns the number of MSR entries actually written.
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///
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///
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fn set_msrs(&self, msrs: &MsrEntries) -> cpu::Result<usize> {
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fn set_msrs(&self, msrs: &[MsrEntry]) -> cpu::Result<usize> {
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let kvm_msrs = MsrEntries::from_entries(msrs).unwrap();
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self.fd
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self.fd
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.set_msrs(msrs)
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.set_msrs(&kvm_msrs)
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.map_err(|e| cpu::HypervisorCpuError::SetMsrEntries(e.into()))
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.map_err(|e| cpu::HypervisorCpuError::SetMsrEntries(e.into()))
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}
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}
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///
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///
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@ -1801,41 +1812,31 @@ impl cpu::Vcpu for KvmVcpu {
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index,
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index,
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..Default::default()
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..Default::default()
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};
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};
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msr_entries.push(msr).unwrap();
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msr_entries.push(msr);
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}
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}
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}
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}
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let expected_num_msrs = msr_entries.as_fam_struct_ref().nmsrs as usize;
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let expected_num_msrs = msr_entries.len();
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let num_msrs = self.get_msrs(&mut msr_entries)?;
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let num_msrs = self.get_msrs(&mut msr_entries)?;
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let msrs = if num_msrs != expected_num_msrs {
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let msrs = if num_msrs != expected_num_msrs {
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let mut faulty_msr_index = num_msrs;
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let mut faulty_msr_index = num_msrs;
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let mut msr_entries_tmp =
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let mut msr_entries_tmp = msr_entries[..faulty_msr_index].to_vec();
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MsrEntries::from_entries(&msr_entries.as_slice()[..faulty_msr_index]).unwrap();
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loop {
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loop {
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warn!(
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warn!(
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"Detected faulty MSR 0x{:x} while getting MSRs",
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"Detected faulty MSR 0x{:x} while getting MSRs",
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msr_entries.as_slice()[faulty_msr_index].index
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msr_entries[faulty_msr_index].index
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);
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);
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// Skip the first bad MSR
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let start_pos = faulty_msr_index + 1;
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let start_pos = faulty_msr_index + 1;
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let mut sub_msr_entries =
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MsrEntries::from_entries(&msr_entries.as_slice()[start_pos..]).unwrap();
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let mut sub_msr_entries = msr_entries[start_pos..].to_vec();
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let expected_num_msrs = sub_msr_entries.as_fam_struct_ref().nmsrs as usize;
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let num_msrs = self.get_msrs(&mut sub_msr_entries)?;
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let num_msrs = self.get_msrs(&mut sub_msr_entries)?;
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for i in 0..num_msrs {
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msr_entries_tmp.extend(&sub_msr_entries[..num_msrs]);
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msr_entries_tmp
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.push(sub_msr_entries.as_slice()[i])
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.map_err(|e| {
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cpu::HypervisorCpuError::GetMsrEntries(anyhow!(
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"Failed adding MSR entries: {:?}",
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e
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))
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})?;
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}
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if num_msrs == expected_num_msrs {
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if num_msrs == sub_msr_entries.len() {
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break;
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break;
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}
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}
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@ -1934,7 +1935,7 @@ impl cpu::Vcpu for KvmVcpu {
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// expected amount, we fallback onto a slower method by setting MSRs
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// expected amount, we fallback onto a slower method by setting MSRs
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// by chunks. This is the only way to make sure we try to set as many
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// by chunks. This is the only way to make sure we try to set as many
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// MSRs as possible, even if some MSRs are not supported.
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// MSRs as possible, even if some MSRs are not supported.
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let expected_num_msrs = state.msrs.as_fam_struct_ref().nmsrs as usize;
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let expected_num_msrs = state.msrs.len();
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let num_msrs = self.set_msrs(&state.msrs)?;
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let num_msrs = self.set_msrs(&state.msrs)?;
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if num_msrs != expected_num_msrs {
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if num_msrs != expected_num_msrs {
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let mut faulty_msr_index = num_msrs;
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let mut faulty_msr_index = num_msrs;
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@ -1942,16 +1943,17 @@ impl cpu::Vcpu for KvmVcpu {
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loop {
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loop {
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warn!(
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warn!(
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"Detected faulty MSR 0x{:x} while setting MSRs",
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"Detected faulty MSR 0x{:x} while setting MSRs",
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state.msrs.as_slice()[faulty_msr_index].index
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state.msrs[faulty_msr_index].index
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);
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);
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// Skip the first bad MSR
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let start_pos = faulty_msr_index + 1;
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let start_pos = faulty_msr_index + 1;
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let sub_msr_entries =
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MsrEntries::from_entries(&state.msrs.as_slice()[start_pos..]).unwrap();
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let sub_msr_entries = state.msrs[start_pos..].to_vec();
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let expected_num_msrs = sub_msr_entries.as_fam_struct_ref().nmsrs as usize;
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let num_msrs = self.set_msrs(&sub_msr_entries)?;
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let num_msrs = self.set_msrs(&sub_msr_entries)?;
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if num_msrs == expected_num_msrs {
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if num_msrs == sub_msr_entries.len() {
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break;
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break;
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}
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}
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@ -2032,11 +2034,10 @@ impl cpu::Vcpu for KvmVcpu {
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///
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///
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/// Return the list of initial MSR entries for a VCPU
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/// Return the list of initial MSR entries for a VCPU
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///
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///
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fn boot_msr_entries(&self) -> MsrEntries {
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fn boot_msr_entries(&self) -> Vec<MsrEntry> {
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use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
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use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
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use kvm_bindings::kvm_msr_entry as MsrEntry;
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MsrEntries::from_entries(&[
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[
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msr!(msr_index::MSR_IA32_SYSENTER_CS),
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msr!(msr_index::MSR_IA32_SYSENTER_CS),
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msr!(msr_index::MSR_IA32_SYSENTER_ESP),
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msr!(msr_index::MSR_IA32_SYSENTER_ESP),
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msr!(msr_index::MSR_IA32_SYSENTER_EIP),
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msr!(msr_index::MSR_IA32_SYSENTER_EIP),
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@ -2051,8 +2052,8 @@ impl cpu::Vcpu for KvmVcpu {
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msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64
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msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64
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),
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),
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msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
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msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
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])
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]
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.unwrap()
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.to_vec()
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}
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}
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}
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}
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@ -55,7 +55,7 @@ pub fn check_required_kvm_extensions(kvm: &Kvm) -> KvmResult<()> {
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#[derive(Clone, Serialize, Deserialize)]
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#[derive(Clone, Serialize, Deserialize)]
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pub struct VcpuKvmState {
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pub struct VcpuKvmState {
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pub cpuid: Vec<CpuIdEntry>,
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pub cpuid: Vec<CpuIdEntry>,
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pub msrs: MsrEntries,
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pub msrs: Vec<MsrEntry>,
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pub vcpu_events: VcpuEvents,
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pub vcpu_events: VcpuEvents,
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pub regs: kvm_regs,
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pub regs: kvm_regs,
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pub sregs: kvm_sregs,
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pub sregs: kvm_sregs,
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@ -229,11 +229,15 @@ impl hypervisor::Hypervisor for MshvHypervisor {
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let msr_list = self.get_msr_list()?;
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let msr_list = self.get_msr_list()?;
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let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
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let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
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let mut msrs = MsrEntries::new(num_msrs).unwrap();
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let mut msrs: Vec<MsrEntry> = vec![
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MsrEntry {
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..Default::default()
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};
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num_msrs
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];
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let indices = msr_list.as_slice();
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let indices = msr_list.as_slice();
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let msr_entries = msrs.as_mut_slice();
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for (pos, index) in indices.iter().enumerate() {
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for (pos, index) in indices.iter().enumerate() {
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msr_entries[pos].index = *index;
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msrs[pos].index = *index;
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}
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}
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let vm_fd = Arc::new(fd);
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let vm_fd = Arc::new(fd);
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@ -258,7 +262,7 @@ pub struct MshvVcpu {
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fd: VcpuFd,
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fd: VcpuFd,
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vp_index: u8,
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vp_index: u8,
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cpuid: Vec<CpuIdEntry>,
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cpuid: Vec<CpuIdEntry>,
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msrs: MsrEntries,
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msrs: Vec<MsrEntry>,
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vm_ops: Option<Arc<dyn vm::VmOps>>,
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vm_ops: Option<Arc<dyn vm::VmOps>>,
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}
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}
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@ -341,19 +345,26 @@ impl cpu::Vcpu for MshvVcpu {
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///
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///
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/// Returns the model-specific registers (MSR) for this vCPU.
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/// Returns the model-specific registers (MSR) for this vCPU.
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///
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///
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fn get_msrs(&self, msrs: &mut MsrEntries) -> cpu::Result<usize> {
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fn get_msrs(&self, msrs: &mut Vec<MsrEntry>) -> cpu::Result<usize> {
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self.fd
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let mut mshv_msrs = MsrEntries::from_entries(msrs).unwrap();
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.get_msrs(msrs)
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let succ = self
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.map_err(|e| cpu::HypervisorCpuError::GetMsrEntries(e.into()))
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.fd
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.get_msrs(&mut mshv_msrs)
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.map_err(|e| cpu::HypervisorCpuError::GetMsrEntries(e.into()))?;
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msrs[..succ].copy_from_slice(&mshv_msrs.as_slice()[..succ]);
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Ok(succ)
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}
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}
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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///
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///
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/// Setup the model-specific registers (MSR) for this vCPU.
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/// Setup the model-specific registers (MSR) for this vCPU.
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/// Returns the number of MSR entries actually written.
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/// Returns the number of MSR entries actually written.
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///
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///
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fn set_msrs(&self, msrs: &MsrEntries) -> cpu::Result<usize> {
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fn set_msrs(&self, msrs: &[MsrEntry]) -> cpu::Result<usize> {
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let mshv_msrs = MsrEntries::from_entries(msrs).unwrap();
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self.fd
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self.fd
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.set_msrs(msrs)
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.set_msrs(&mshv_msrs)
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.map_err(|e| cpu::HypervisorCpuError::SetMsrEntries(e.into()))
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.map_err(|e| cpu::HypervisorCpuError::SetMsrEntries(e.into()))
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}
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}
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@ -655,10 +666,10 @@ impl cpu::Vcpu for MshvVcpu {
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///
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///
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/// Return the list of initial MSR entries for a VCPU
|
/// Return the list of initial MSR entries for a VCPU
|
||||||
///
|
///
|
||||||
fn boot_msr_entries(&self) -> MsrEntries {
|
fn boot_msr_entries(&self) -> Vec<MsrEntry> {
|
||||||
use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
|
use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB};
|
||||||
|
|
||||||
MsrEntries::from_entries(&[
|
[
|
||||||
msr!(msr_index::MSR_IA32_SYSENTER_CS),
|
msr!(msr_index::MSR_IA32_SYSENTER_CS),
|
||||||
msr!(msr_index::MSR_IA32_SYSENTER_ESP),
|
msr!(msr_index::MSR_IA32_SYSENTER_ESP),
|
||||||
msr!(msr_index::MSR_IA32_SYSENTER_EIP),
|
msr!(msr_index::MSR_IA32_SYSENTER_EIP),
|
||||||
@ -669,8 +680,8 @@ impl cpu::Vcpu for MshvVcpu {
|
|||||||
msr!(msr_index::MSR_SYSCALL_MASK),
|
msr!(msr_index::MSR_SYSCALL_MASK),
|
||||||
msr!(msr_index::MSR_IA32_TSC),
|
msr!(msr_index::MSR_IA32_TSC),
|
||||||
msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
|
msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
|
||||||
])
|
]
|
||||||
.unwrap()
|
.to_vec()
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -888,7 +899,7 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
|
|||||||
/// Wrapper over Mshv VM ioctls.
|
/// Wrapper over Mshv VM ioctls.
|
||||||
pub struct MshvVm {
|
pub struct MshvVm {
|
||||||
fd: Arc<VmFd>,
|
fd: Arc<VmFd>,
|
||||||
msrs: MsrEntries,
|
msrs: Vec<MsrEntry>,
|
||||||
vm_ops: Option<Arc<dyn vm::VmOps>>,
|
vm_ops: Option<Arc<dyn vm::VmOps>>,
|
||||||
dirty_log_slots: Arc<RwLock<HashMap<u64, MshvDirtyLogSlot>>>,
|
dirty_log_slots: Arc<RwLock<HashMap<u64, MshvDirtyLogSlot>>>,
|
||||||
}
|
}
|
||||||
|
@ -32,7 +32,7 @@ pub use {
|
|||||||
|
|
||||||
#[derive(Clone, Serialize, Deserialize)]
|
#[derive(Clone, Serialize, Deserialize)]
|
||||||
pub struct VcpuMshvState {
|
pub struct VcpuMshvState {
|
||||||
pub msrs: MsrEntries,
|
pub msrs: Vec<MsrEntry>,
|
||||||
pub vcpu_events: VcpuEvents,
|
pub vcpu_events: VcpuEvents,
|
||||||
pub regs: MshvStandardRegisters,
|
pub regs: MshvStandardRegisters,
|
||||||
pub sregs: MshvSpecialRegisters,
|
pub sregs: MshvSpecialRegisters,
|
||||||
@ -46,10 +46,10 @@ pub struct VcpuMshvState {
|
|||||||
|
|
||||||
impl fmt::Display for VcpuMshvState {
|
impl fmt::Display for VcpuMshvState {
|
||||||
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
||||||
let expected_num_msrs = self.msrs.as_fam_struct_ref().nmsrs as usize;
|
let expected_num_msrs = self.msrs.len();
|
||||||
let mut msr_entries = vec![vec![0; 2]; expected_num_msrs];
|
let mut msr_entries = vec![vec![0; 2]; expected_num_msrs];
|
||||||
|
|
||||||
for (i, entry) in self.msrs.as_slice().iter().enumerate() {
|
for (i, entry) in self.msrs.iter().enumerate() {
|
||||||
msr_entries[i][1] = entry.data;
|
msr_entries[i][1] = entry.data;
|
||||||
msr_entries[i][0] = entry.index as u64;
|
msr_entries[i][0] = entry.index as u64;
|
||||||
}
|
}
|
||||||
|
@ -45,7 +45,7 @@ use hypervisor::kvm::kvm_bindings;
|
|||||||
#[cfg(feature = "tdx")]
|
#[cfg(feature = "tdx")]
|
||||||
use hypervisor::kvm::{TdxExitDetails, TdxExitStatus};
|
use hypervisor::kvm::{TdxExitDetails, TdxExitStatus};
|
||||||
#[cfg(feature = "guest_debug")]
|
#[cfg(feature = "guest_debug")]
|
||||||
use hypervisor::x86_64::{MsrEntries, MsrEntry};
|
use hypervisor::x86_64::MsrEntry;
|
||||||
use hypervisor::{CpuState, HypervisorCpuError, VmExit, VmOps};
|
use hypervisor::{CpuState, HypervisorCpuError, VmExit, VmOps};
|
||||||
use libc::{c_void, siginfo_t};
|
use libc::{c_void, siginfo_t};
|
||||||
#[cfg(feature = "guest_debug")]
|
#[cfg(feature = "guest_debug")]
|
||||||
@ -2271,11 +2271,10 @@ impl CpuElf64Writable for CpuManager {
|
|||||||
.get_sregs()
|
.get_sregs()
|
||||||
.map_err(|_e| GuestDebuggableError::Coredump(anyhow!("get sregs failed")))?;
|
.map_err(|_e| GuestDebuggableError::Coredump(anyhow!("get sregs failed")))?;
|
||||||
|
|
||||||
let mut msrs = MsrEntries::from_entries(&[MsrEntry {
|
let mut msrs = vec![MsrEntry {
|
||||||
index: msr_index::MSR_KERNEL_GS_BASE,
|
index: msr_index::MSR_KERNEL_GS_BASE,
|
||||||
..Default::default()
|
..Default::default()
|
||||||
}])
|
}];
|
||||||
.map_err(|_e| GuestDebuggableError::Coredump(anyhow!("get msr failed")))?;
|
|
||||||
|
|
||||||
self.vcpus[vcpu_id as usize]
|
self.vcpus[vcpu_id as usize]
|
||||||
.lock()
|
.lock()
|
||||||
@ -2283,7 +2282,7 @@ impl CpuElf64Writable for CpuManager {
|
|||||||
.vcpu
|
.vcpu
|
||||||
.get_msrs(&mut msrs)
|
.get_msrs(&mut msrs)
|
||||||
.map_err(|_e| GuestDebuggableError::Coredump(anyhow!("get msr failed")))?;
|
.map_err(|_e| GuestDebuggableError::Coredump(anyhow!("get msr failed")))?;
|
||||||
let kernel_gs_base = msrs.as_slice()[0].data;
|
let kernel_gs_base = msrs[0].data;
|
||||||
|
|
||||||
let cs = CpuSegment::new(sregs.cs);
|
let cs = CpuSegment::new(sregs.cs);
|
||||||
let ds = CpuSegment::new(sregs.ds);
|
let ds = CpuSegment::new(sregs.ds);
|
||||||
@ -2389,7 +2388,7 @@ mod tests {
|
|||||||
#[test]
|
#[test]
|
||||||
fn test_setup_msrs() {
|
fn test_setup_msrs() {
|
||||||
use hypervisor::arch::x86::msr_index;
|
use hypervisor::arch::x86::msr_index;
|
||||||
use hypervisor::x86_64::{MsrEntries, MsrEntry};
|
use hypervisor::x86_64::MsrEntry;
|
||||||
|
|
||||||
let hv = hypervisor::new().unwrap();
|
let hv = hypervisor::new().unwrap();
|
||||||
let vm = hv.create_vm().expect("new VM fd creation failed");
|
let vm = hv.create_vm().expect("new VM fd creation failed");
|
||||||
@ -2398,11 +2397,10 @@ mod tests {
|
|||||||
|
|
||||||
// This test will check against the last MSR entry configured (the tenth one).
|
// This test will check against the last MSR entry configured (the tenth one).
|
||||||
// See create_msr_entries for details.
|
// See create_msr_entries for details.
|
||||||
let mut msrs = MsrEntries::from_entries(&[MsrEntry {
|
let mut msrs = vec![MsrEntry {
|
||||||
index: msr_index::MSR_IA32_MISC_ENABLE,
|
index: msr_index::MSR_IA32_MISC_ENABLE,
|
||||||
..Default::default()
|
..Default::default()
|
||||||
}])
|
}];
|
||||||
.unwrap();
|
|
||||||
|
|
||||||
// get_msrs returns the number of msrs that it succeed in reading. We only want to read 1
|
// get_msrs returns the number of msrs that it succeed in reading. We only want to read 1
|
||||||
// in this test case scenario.
|
// in this test case scenario.
|
||||||
|
Loading…
Reference in New Issue
Block a user