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virtio-devices: transport: Remove unnecessary mut from reference

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warning: this argument is a mutable reference, but not used mutably
   --> virtio-devices/src/transport/pci_common_config.rs💯17
    |
100 |         queues: &mut [Queue],
    |                 ^^^^^^^^^^^^ help: consider changing to: `&[Queue]`
    |
    = warning: changing this function will impact semver compatibility
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#needless_pass_by_ref_mut
    = note: `#[warn(clippy::needless_pass_by_ref_mut)]` on by default

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
This commit is contained in:
Rob Bradford 2023-08-22 10:48:26 +01:00 committed by Rob Bradford
parent cc4422d58b
commit 4d8dacec5e
2 changed files with 8 additions and 8 deletions
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14
virtio-devices/src/transport/pci_common_config.rs
View File

@ -97,7 +97,7 @@ impl VirtioPciCommonConfig {
&mut self,
offset: u64,
data: &mut [u8],
queues: &mut [Queue],
queues: &[Queue],
device: Arc<Mutex<dyn VirtioDevice>>,
) {
assert!(data.len() <= 8);
@ -385,35 +385,35 @@ mod tests {
// Can set all bits of driver_status.
regs.write(0x14, &[0x55], &mut queues, dev.clone());
let mut read_back = vec![0x00];
regs.read(0x14, &mut read_back, &mut queues, dev.clone());
regs.read(0x14, &mut read_back, &queues, dev.clone());
assert_eq!(read_back[0], 0x55);
// The config generation register is read only.
regs.write(0x15, &[0xaa], &mut queues, dev.clone());
let mut read_back = vec![0x00];
regs.read(0x15, &mut read_back, &mut queues, dev.clone());
regs.read(0x15, &mut read_back, &queues, dev.clone());
assert_eq!(read_back[0], 0x55);
// Device features is read-only and passed through from the device.
regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev.clone());
let mut read_back = vec![0, 0, 0, 0];
regs.read(0x04, &mut read_back, &mut queues, dev.clone());
regs.read(0x04, &mut read_back, &queues, dev.clone());
assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
// Feature select registers are read/write.
regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev.clone());
let mut read_back = vec![0, 0, 0, 0];
regs.read(0x00, &mut read_back, &mut queues, dev.clone());
regs.read(0x00, &mut read_back, &queues, dev.clone());
assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev.clone());
let mut read_back = vec![0, 0, 0, 0];
regs.read(0x08, &mut read_back, &mut queues, dev.clone());
regs.read(0x08, &mut read_back, &queues, dev.clone());
assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
// 'queue_select' can be read and written.
regs.write(0x16, &[0xaa, 0x55], &mut queues, dev.clone());
let mut read_back = vec![0x00, 0x00];
regs.read(0x16, &mut read_back, &mut queues, dev);
regs.read(0x16, &mut read_back, &queues, dev);
assert_eq!(read_back[0], 0xaa);
assert_eq!(read_back[1], 0x55);
}

2
virtio-devices/src/transport/pci_device.rs
View File

@ -1116,7 +1116,7 @@ impl PciDevice for VirtioPciDevice {
o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.read(
o - COMMON_CONFIG_BAR_OFFSET,
data,
&mut self.queues,
&self.queues,
self.device.clone(),
),
o if (ISR_CONFIG_BAR_OFFSET..ISR_CONFIG_BAR_OFFSET + ISR_CONFIG_SIZE).contains(&o) => {