From 5432cbfaad9b32e33cad5993d9502e02c3bb6a1e Mon Sep 17 00:00:00 2001 From: Muminul Islam Date: Tue, 22 Jun 2021 11:35:02 -0700 Subject: [PATCH] hypervisor: Set MTRRdefType in MSHV guest initialization to enable cpu caching Initialize MTRR defType register the same way the KVM code does - WB caching by default. Tested with latest mshv code. Without this patch, these lines are present in guest serial log: [ 0.000032] x86/PAT: MTRRs disabled, skipping PAT initialization too. [ 0.000036] CPU MTRRs all blank - virtualized system. This indicates the guest is detecting the set MTRR. Signed-off-by: Nuno Das Neves Signed-off-by: Muminul Islam --- hypervisor/src/mshv/x86_64/mod.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hypervisor/src/mshv/x86_64/mod.rs b/hypervisor/src/mshv/x86_64/mod.rs index d072e9a13..e1a204945 100644 --- a/hypervisor/src/mshv/x86_64/mod.rs +++ b/hypervisor/src/mshv/x86_64/mod.rs @@ -8,7 +8,7 @@ // // -use crate::arch::x86::{msr_index, SegmentRegisterOps}; +use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; use serde_derive::{Deserialize, Serialize}; /// /// Export generically-named wrappers of mshv_bindings for Unix-based platforms @@ -118,6 +118,7 @@ pub fn boot_msr_entries() -> MsrEntries { msr!(msr_index::MSR_KERNEL_GS_BASE), msr!(msr_index::MSR_SYSCALL_MASK), msr!(msr_index::MSR_IA32_TSC), + msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), ]) .unwrap() }