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arch: x86_64: acpi: Generate DSDT programatically
This was verified by comparing the ASL from disassembling the DSDT before and after. All the individual AML components themselves are also unit tested. Fixes: #352 Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
parent
dd539df633
commit
555ac68ea5
@ -3,6 +3,8 @@
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// SPDX-License-Identifier: Apache-2.0
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//
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use acpi_tables::{
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aml,
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aml::Aml,
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rsdp::RSDP,
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sdt::{GenericAddress, SDT},
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};
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@ -111,186 +113,90 @@ pub fn create_dsdt_table(
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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) -> SDT {
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/*
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The hex tables in this file are generated from the ASL below with:
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"iasl -tc <dsdt.asl>"
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let pci_dsdt_data = aml::Device::new(
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"_SB_.PCI0".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0A08")),
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&aml::Name::new("_CID".into(), &aml::EISAName::new("PNP0A03")),
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&aml::Name::new("_ADR".into(), &aml::ZERO),
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&aml::Name::new("_SEG".into(), &aml::ZERO),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new("SUPP".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0xffu16),
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&aml::IO::new(0xcf8, 0xcf8, 1, 0x8),
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&aml::AddressSpace::new_io(0x0u16, 0xcf7u16),
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&aml::AddressSpace::new_io(0xd00u16, 0xffffu16),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::Cacheable,
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true,
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0xa_0000u32,
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0xb_ffffu32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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layout::MEM_32BIT_DEVICES_START.0 as u32,
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(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1)
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as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::Cacheable,
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true,
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start_of_device_area.0,
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end_of_device_area.0,
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),
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]),
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),
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],
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)
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.to_bytes();
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As the output contains a table header that is not required the first 36 bytes
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should be disregarded.
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*/
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let mbrd_dsdt_data = aml::Device::new(
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"_SB_.MBRD".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0C02")),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::Memory32Fixed::new(
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true,
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layout::PCI_MMCONFIG_START.0 as u32,
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layout::PCI_MMCONFIG_SIZE as u32,
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)]),
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),
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],
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)
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.to_bytes();
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/*
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Device (_SB.PCI0)
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{
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Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
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Name (_ADR, Zero) // _ADR: Address
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Name (_SEG, Zero) // _SEG: PCI Segment
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Name (_UID, Zero) // _UID: Unique ID
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Name (SUPP, Zero)
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}
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let com1_dsdt_data = aml::Device::new(
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"_SB_.COM1".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0501")),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::Interrupt::new(true, true, false, false, 4),
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&aml::IO::new(0x3f8, 0x3f8, 0, 0x8),
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]),
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),
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],
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)
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.to_bytes();
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Scope (_SB.PCI0)
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{
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Granularity
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0x0000, // Range Minimum
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0x00FF, // Range Maximum
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0x0000, // Translation Offset
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0x0100, // Length
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,, )
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IO (Decode16,
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0x0CF8, // Range Minimum
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0x0CF8, // Range Maximum
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0x01, // Alignment
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0x08, // Length
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)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Granularity
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0x0000, // Range Minimum
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0x0CF7, // Range Maximum
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0x0000, // Translation Offset
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0x0CF8, // Length
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,, , TypeStatic, DenseTranslation)
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Granularity
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0x0D00, // Range Minimum
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0xFFFF, // Range Maximum
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0x0000, // Translation Offset
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0xF300, // Length
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,, , TypeStatic, DenseTranslation)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Granularity
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0x000A0000, // Range Minimum
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0x000BFFFF, // Range Maximum
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0x00000000, // Translation Offset
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0x00020000, // Length
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,, , AddressRangeMemory, TypeStatic)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Granularity
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0xC0000000, // Range Minimum
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0xFEBFFFFF, // Range Maximum
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0x00000000, // Translation Offset
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0x3EC00000, // Length
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,, , AddressRangeMemory, TypeStatic)
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x0000000000000000, // Granularity
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0x0000000800000000, // Range Minimum
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0x0000000FFFFFFFFF, // Range Maximum
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0x0000000000000000, // Translation Offset
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0x0000000800000000, // Length
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,, , AddressRangeMemory, TypeStatic)
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})
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}
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*/
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let mut pci_dsdt_data = [
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0x5Bu8, 0x82, 0x36, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x50, 0x43, 0x49, 0x30, 0x08, 0x5F, 0x48,
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0x49, 0x44, 0x0C, 0x41, 0xD0, 0x0A, 0x08, 0x08, 0x5F, 0x43, 0x49, 0x44, 0x0C, 0x41, 0xD0,
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0x0A, 0x03, 0x08, 0x5F, 0x41, 0x44, 0x52, 0x00, 0x08, 0x5F, 0x53, 0x45, 0x47, 0x00, 0x08,
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0x5F, 0x55, 0x49, 0x44, 0x00, 0x08, 0x53, 0x55, 0x50, 0x50, 0x00, 0x10, 0x41, 0x0B, 0x2E,
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0x5F, 0x53, 0x42, 0x5F, 0x50, 0x43, 0x49, 0x30, 0x08, 0x5F, 0x43, 0x52, 0x53, 0x11, 0x40,
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0x0A, 0x0A, 0x9C, 0x88, 0x0D, 0x00, 0x02, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x47, 0x01, 0xF8, 0x0C, 0xF8, 0x0C, 0x01, 0x08, 0x88, 0x0D, 0x00,
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0x01, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF7, 0x0C, 0x00, 0x00, 0xF8, 0x0C, 0x88, 0x0D,
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0x00, 0x01, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x0D, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xF3, 0x87,
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0x17, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0xFF, 0xFF,
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0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x87, 0x17, 0x00, 0x00, 0x0C,
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0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xBF, 0xFE, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0xC0, 0x3E, 0x8A, 0x2B, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0xFF, 0xFF,
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0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x79, 0x00,
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];
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// Patch Range Minimum/Range Maximum/Length for the the 64-bit device area
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pci_dsdt_data[170..174].copy_from_slice(&layout::MEM_32BIT_DEVICES_START.0.to_le_bytes()[0..4]);
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pci_dsdt_data[174..178].copy_from_slice(
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&(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1).to_le_bytes()
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[0..4],
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);
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pci_dsdt_data[182..186].copy_from_slice(&layout::MEM_32BIT_DEVICES_SIZE.to_le_bytes()[0..4]);
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// Patch the Range Minimum/Range Maximum/Length for the the 64-bit device area
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pci_dsdt_data[200..208].copy_from_slice(&(start_of_device_area.0).to_le_bytes());
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pci_dsdt_data[208..216].copy_from_slice(&end_of_device_area.0.to_le_bytes());
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pci_dsdt_data[224..232].copy_from_slice(
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&(end_of_device_area.unchecked_offset_from(start_of_device_area) + 1).to_le_bytes(),
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);
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/*
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Device (_SB.MBRD)
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{
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Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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}
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Scope (_SB.MBRD)
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{
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Memory32Fixed (ReadWrite,
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0xE8000000, // Address Base
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0x10000000, // Address Length
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)
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})
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}
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*/
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let mut mbrd_dsdt_data = [
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0x5Bu8, 0x82, 0x1A, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x4D, 0x42, 0x52, 0x44, 0x08, 0x5F, 0x48,
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0x49, 0x44, 0x0C, 0x41, 0xD0, 0x0C, 0x02, 0x08, 0x5F, 0x55, 0x49, 0x44, 0x00, 0x10, 0x21,
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0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x4D, 0x42, 0x52, 0x44, 0x08, 0x5F, 0x43, 0x52, 0x53, 0x11,
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0x11, 0x0A, 0x0E, 0x86, 0x09, 0x00, 0x01, 0x00, 0x00, 0x00, 0xE8, 0x00, 0x00, 0x00, 0x10,
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0x79, 0x00,
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];
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mbrd_dsdt_data[52..56].copy_from_slice(&layout::PCI_MMCONFIG_START.0.to_le_bytes()[0..4]);
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mbrd_dsdt_data[56..60].copy_from_slice(&layout::PCI_MMCONFIG_SIZE.to_le_bytes()[0..4]);
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/*
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Device (_SB.COM1)
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{
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Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
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{
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0x00000004,
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}
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IO (Decode16,
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0x03F8, // Range Minimum
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0x03F8, // Range Maximum
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0x00, // Alignment
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0x08, // Length
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)
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})
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}
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*/
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let com1_dsdt_data = [
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0x5Bu8, 0x82, 0x36, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x43, 0x4F, 0x4D, 0x31, 0x08, 0x5F, 0x48,
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0x49, 0x44, 0x0C, 0x41, 0xD0, 0x05, 0x01, 0x08, 0x5F, 0x55, 0x49, 0x44, 0x00, 0x08, 0x5F,
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0x43, 0x52, 0x53, 0x11, 0x16, 0x0A, 0x13, 0x89, 0x06, 0x00, 0x03, 0x01, 0x04, 0x00, 0x00,
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0x00, 0x47, 0x01, 0xF8, 0x03, 0xF8, 0x03, 0x00, 0x08, 0x79, 0x00,
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];
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/*
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Name (\_S5, Package (0x01) // _S5_: S5 System State
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{
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0x05
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})
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*/
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let s5_sleep_data = [0x08u8, 0x5F, 0x53, 0x35, 0x5F, 0x12, 0x04, 0x01, 0x0A, 0x05];
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let s5_sleep_data = aml::Name::new("_S5_".into(), &aml::Package::new(vec![&5u8])).to_bytes();
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// DSDT
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let mut dsdt = SDT::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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dsdt.append(pci_dsdt_data);
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dsdt.append(mbrd_dsdt_data);
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dsdt.append_slice(pci_dsdt_data.as_slice());
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dsdt.append_slice(mbrd_dsdt_data.as_slice());
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if serial_enabled {
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dsdt.append(com1_dsdt_data);
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dsdt.append_slice(com1_dsdt_data.as_slice());
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}
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dsdt.append(s5_sleep_data);
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dsdt.append_slice(s5_sleep_data.as_slice());
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dsdt
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}
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