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hypervisor: x86: emulator: test executing only one instruction
Signed-off-by: Wei Liu <liuwe@microsoft.com>
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@ -840,6 +840,52 @@ mod tests {
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assert_eq!(rbx, target_rax);
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}
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#[test]
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// Emulate only one instruction.
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//
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// mov rax, 0x1000
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// mov rbx, qword ptr [rax+10h]
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// The emulation should stop after the first instruction.
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fn test_emulate_one_instruction() {
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let target_rax: u64 = 0x1000;
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let ip: u64 = 0x1000;
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let cpu_id = 0;
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let memory = [
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// Code at IP
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0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000
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0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
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// Padding
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0x00, 0x00, 0x00, 0x00, 0x00, // Padding is all zeroes
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// Data at IP + 0x10 (0x1234567812345678 in LE)
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0x78, 0x56, 0x34, 0x12, 0x78, 0x56, 0x34, 0x12,
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];
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let insn = [
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0x48, 0xc7, 0xc0, 0x00, 0x10, 0x00, 0x00, // mov rax, 0x1000
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0x48, 0x8b, 0x58, 0x10, // mov rbx, qword ptr [rax+10h]
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];
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let mut vmm = MockVmm::new(ip, vec![], Some((ip, &memory)));
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assert!(vmm.emulate_insn(cpu_id, &insn, Some(1)).is_ok());
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let new_ip: u64 = vmm.cpu_state(cpu_id).unwrap().ip();
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assert_eq!(new_ip, ip + 0x7 /* length of mov rax,0x1000 */);
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let rax: u64 = vmm
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.cpu_state(cpu_id)
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.unwrap()
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.read_reg(Register::RAX)
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.unwrap();
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assert_eq!(rax, target_rax);
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// The second instruction is not executed so RBX should be zero.
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let rbx: u64 = vmm
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.cpu_state(cpu_id)
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.unwrap()
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.read_reg(Register::RBX)
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.unwrap();
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assert_eq!(rbx, 0);
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}
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#[test]
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// Emulate truncated instruction stream, which should cause a fetch.
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//
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