From 5e937c8b88865080c107a99b3a44b94c6aa2bb1f Mon Sep 17 00:00:00 2001
From: Ruoqing He <heruoqing@iscas.ac.cn>
Date: Wed, 9 Oct 2024 21:13:26 +0800
Subject: [PATCH] hypervisor: vm: Introduce RISC-V Vm trait

Introduce RISC-V specific Vm traits and error variant, disable
`create_irq_chip` on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
---
 hypervisor/src/vm.rs | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/hypervisor/src/vm.rs b/hypervisor/src/vm.rs
index 356cf4172..2d45a8d9e 100644
--- a/hypervisor/src/vm.rs
+++ b/hypervisor/src/vm.rs
@@ -1,3 +1,5 @@
+// Copyright © 2024 Institute of Software, CAS. All rights reserved.
+//
 // Copyright © 2019 Intel Corporation
 //
 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
@@ -12,7 +14,7 @@ use std::any::Any;
 #[cfg(target_arch = "x86_64")]
 use std::fs::File;
 use std::sync::Arc;
-#[cfg(target_arch = "aarch64")]
+#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))]
 use std::sync::Mutex;
 
 #[cfg(feature = "sev_snp")]
@@ -24,6 +26,8 @@ use vmm_sys_util::eventfd::EventFd;
 use crate::aarch64::VcpuInit;
 #[cfg(target_arch = "aarch64")]
 use crate::arch::aarch64::gic::{Vgic, VgicConfig};
+#[cfg(target_arch = "riscv64")]
+use crate::arch::riscv64::aia::{Vaia, VaiaConfig};
 #[cfg(feature = "tdx")]
 use crate::arch::x86::CpuIdEntry;
 use crate::cpu::Vcpu;
@@ -224,6 +228,11 @@ pub enum HypervisorVmError {
     #[error("Failed to create Vgic: {0}")]
     CreateVgic(#[source] anyhow::Error),
     ///
+    /// Create Vaia error
+    ///
+    #[error("Failed to create Vaia: {0}")]
+    CreateVaia(#[source] anyhow::Error),
+    ///
     /// Import isolated pages error
     ///
     #[error("Failed to import isolated pages: {0}")]
@@ -293,6 +302,7 @@ pub trait Vm: Send + Sync + Any {
     #[cfg(target_arch = "x86_64")]
     /// Sets the address of the three-page region in the VM's address space.
     fn set_tss_address(&self, offset: usize) -> Result<()>;
+    #[cfg(not(target_arch = "riscv64"))]
     /// Creates an in-kernel interrupt controller.
     fn create_irq_chip(&self) -> Result<()>;
     /// Registers an event that will, when signaled, trigger the `gsi` IRQ.
@@ -303,6 +313,8 @@ pub trait Vm: Send + Sync + Any {
     fn create_vcpu(&self, id: u8, vm_ops: Option<Arc<dyn VmOps>>) -> Result<Arc<dyn Vcpu>>;
     #[cfg(target_arch = "aarch64")]
     fn create_vgic(&self, config: VgicConfig) -> Result<Arc<Mutex<dyn Vgic>>>;
+    #[cfg(target_arch = "riscv64")]
+    fn create_vaia(&self, config: VaiaConfig) -> Result<Arc<Mutex<dyn Vaia>>>;
 
     /// Registers an event to be signaled whenever a certain address is written to.
     fn register_ioevent(