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hypervisor: vm: Introduce RISC-V Vm trait

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Introduce RISC-V specific Vm traits and error variant, disable
`create_irq_chip` on RISC-V platform.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
This commit is contained in:
Ruoqing He 2024-10-09 21:13:26 +08:00 committed by Rob Bradford
parent 710535343b
commit 5e937c8b88
1 changed files with 13 additions and 1 deletions
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14
hypervisor/src/vm.rs
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@ -1,3 +1,5 @@
// Copyright © 2024 Institute of Software, CAS. All rights reserved.
//
// Copyright © 2019 Intel Corporation // Copyright © 2019 Intel Corporation
// //
// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
@ -12,7 +14,7 @@ use std::any::Any;
#[cfg(target_arch = "x86_64")] #[cfg(target_arch = "x86_64")]
use std::fs::File; use std::fs::File;
use std::sync::Arc; use std::sync::Arc;
#[cfg(target_arch = "aarch64")] #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))]
use std::sync::Mutex; use std::sync::Mutex;
#[cfg(feature = "sev_snp")] #[cfg(feature = "sev_snp")]
@ -24,6 +26,8 @@ use vmm_sys_util::eventfd::EventFd;
use crate::aarch64::VcpuInit; use crate::aarch64::VcpuInit;
#[cfg(target_arch = "aarch64")] #[cfg(target_arch = "aarch64")]
use crate::arch::aarch64::gic::{Vgic, VgicConfig}; use crate::arch::aarch64::gic::{Vgic, VgicConfig};
#[cfg(target_arch = "riscv64")]
use crate::arch::riscv64::aia::{Vaia, VaiaConfig};
#[cfg(feature = "tdx")] #[cfg(feature = "tdx")]
use crate::arch::x86::CpuIdEntry; use crate::arch::x86::CpuIdEntry;
use crate::cpu::Vcpu; use crate::cpu::Vcpu;
@ -224,6 +228,11 @@ pub enum HypervisorVmError {
#[error("Failed to create Vgic: {0}")] #[error("Failed to create Vgic: {0}")]
CreateVgic(#[source] anyhow::Error), CreateVgic(#[source] anyhow::Error),
/// ///
/// Create Vaia error
///
#[error("Failed to create Vaia: {0}")]
CreateVaia(#[source] anyhow::Error),
///
/// Import isolated pages error /// Import isolated pages error
/// ///
#[error("Failed to import isolated pages: {0}")] #[error("Failed to import isolated pages: {0}")]
@ -293,6 +302,7 @@ pub trait Vm: Send + Sync + Any {
#[cfg(target_arch = "x86_64")] #[cfg(target_arch = "x86_64")]
/// Sets the address of the three-page region in the VM's address space. /// Sets the address of the three-page region in the VM's address space.
fn set_tss_address(&self, offset: usize) -> Result<()>; fn set_tss_address(&self, offset: usize) -> Result<()>;
#[cfg(not(target_arch = "riscv64"))]
/// Creates an in-kernel interrupt controller. /// Creates an in-kernel interrupt controller.
fn create_irq_chip(&self) -> Result<()>; fn create_irq_chip(&self) -> Result<()>;
/// Registers an event that will, when signaled, trigger the `gsi` IRQ. /// Registers an event that will, when signaled, trigger the `gsi` IRQ.
@ -303,6 +313,8 @@ pub trait Vm: Send + Sync + Any {
fn create_vcpu(&self, id: u8, vm_ops: Option<Arc<dyn VmOps>>) -> Result<Arc<dyn Vcpu>>; fn create_vcpu(&self, id: u8, vm_ops: Option<Arc<dyn VmOps>>) -> Result<Arc<dyn Vcpu>>;
#[cfg(target_arch = "aarch64")] #[cfg(target_arch = "aarch64")]
fn create_vgic(&self, config: VgicConfig) -> Result<Arc<Mutex<dyn Vgic>>>; fn create_vgic(&self, config: VgicConfig) -> Result<Arc<Mutex<dyn Vgic>>>;
#[cfg(target_arch = "riscv64")]
fn create_vaia(&self, config: VaiaConfig) -> Result<Arc<Mutex<dyn Vaia>>>;
/// Registers an event to be signaled whenever a certain address is written to. /// Registers an event to be signaled whenever a certain address is written to.
fn register_ioevent( fn register_ioevent(