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arch: x86_64: Enable CR4 LA57 feature

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In case the host CPU exposes the support for LA57 feature through its
cpuid, the CR4.LA57 bit is enabled accordingly.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2020-06-09 13:43:15 +02:00 committed by Rob Bradford
parent 09fd325963
commit 5f0b620148
1 changed files with 6 additions and 0 deletions
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6
arch/src/x86_64/regs.rs
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@ -138,6 +138,7 @@ const EFER_LME: u64 = 0x100;
const X86_CR0_PE: u64 = 0x1;
const X86_CR0_PG: u64 = 0x80000000;
const X86_CR4_PAE: u64 = 0x20;
const X86_CR4_LA57: u64 = 0x1000;
fn write_gdt_table(table: &[u64], guest_mem: &GuestMemoryMmap) -> Result<()> {
let boot_gdt_addr = BOOT_GDT_START;
@ -239,6 +240,11 @@ fn setup_page_tables(mem: &GuestMemoryMmap, sregs: &mut kvm_sregs) -> Result<()>
sregs.cr3 = PML4_START.raw_value();
sregs.cr4 |= X86_CR4_PAE;
sregs.cr0 |= X86_CR0_PG;
if unsafe { std::arch::x86_64::__cpuid(7).ecx } & (1 << 16) != 0 {
sregs.cr4 |= X86_CR4_LA57;
}
Ok(())
}