pci: Fix #[cfg(target_arch)] guards for port I/O

Port I/O is only supported on x86_64 - use inverted conditional logic to
match the other architectures rather than calling them out specifically.
This will be relevant when RISC-V support is added.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
This commit is contained in:
Rob Bradford 2024-09-20 11:09:01 +01:00 committed by Bo Chen
parent 990ba0666d
commit 60165bbcfa
2 changed files with 4 additions and 4 deletions

View File

@ -134,7 +134,7 @@ impl PciBus {
io_bus io_bus
.insert(dev.clone(), bar.addr(), bar.size()) .insert(dev.clone(), bar.addr(), bar.size())
.map_err(PciRootError::PioInsert)?; .map_err(PciRootError::PioInsert)?;
#[cfg(target_arch = "aarch64")] #[cfg(not(target_arch = "x86_64"))]
error!("I/O region is not supported"); error!("I/O region is not supported");
} }
PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => { PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => {

View File

@ -711,11 +711,11 @@ impl VfioCommon {
let bar_addr = match region_type { let bar_addr = match region_type {
PciBarRegionType::IoRegion => { PciBarRegionType::IoRegion => {
#[cfg(target_arch = "aarch64")] #[cfg(not(target_arch = "x86_64"))]
unimplemented!(); unimplemented!();
// The address needs to be 4 bytes aligned. // The address needs to be 4 bytes aligned.
#[cfg(not(target_arch = "aarch64"))] #[cfg(target_arch = "x86_64")]
allocator allocator
.lock() .lock()
.unwrap() .unwrap()
@ -795,7 +795,7 @@ impl VfioCommon {
PciBarRegionType::IoRegion => { PciBarRegionType::IoRegion => {
#[cfg(target_arch = "x86_64")] #[cfg(target_arch = "x86_64")]
allocator.free_io_addresses(region.start, region.length); allocator.free_io_addresses(region.start, region.length);
#[cfg(target_arch = "aarch64")] #[cfg(not(target_arch = "x86_64"))]
error!("I/O region is not supported"); error!("I/O region is not supported");
} }
PciBarRegionType::Memory32BitRegion => { PciBarRegionType::Memory32BitRegion => {