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pci: vfio: Fix and clarify BAR calculation code
The BAR calculation code was incorrect for calculating I/O BARs but also has misleading comments (mixing bits and bytes, first and least significant, etc). This change adjusts the algorithm to more closely match the version described in the PCI specification and takes advantage of Rust's binary literals for ease of reading. Although this is slightly longer by calculating the 64-bit and 32-bit paths separately I think this is easier to read. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
Sebastien Boeuf
parent
1f2915bff0
commit
6e63df98ba
121
pci/src/vfio.rs
121
pci/src/vfio.rs
@ -788,8 +788,6 @@ const PCI_CONFIG_BAR_OFFSET: u32 = 0x10;
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const PCI_CONFIG_CAPABILITY_OFFSET: u32 = 0x34;
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// IO BAR when first BAR bit is 1.
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const PCI_CONFIG_IO_BAR: u32 = 0x1;
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// Memory BAR flags (lower 4 bits).
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const PCI_CONFIG_MEMORY_BAR_FLAG_MASK: u32 = 0xf;
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// 64-bit memory bar flag.
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const PCI_CONFIG_MEMORY_BAR_64BIT: u32 = 0x4;
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// PCI config register size (4 bytes).
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@ -817,33 +815,21 @@ impl PciDevice for VfioPciDevice {
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// are going to allocate a guest address for each BAR and write
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// that new address back.
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while bar_id < VFIO_PCI_CONFIG_REGION_INDEX {
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let mut lsb_size: u32 = 0xffff_ffff;
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let mut msb_size = 0;
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let mut region_size: u64;
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let region_size: u64;
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let bar_addr: GuestAddress;
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// Read the BAR size (Starts by all 1s to the BAR)
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let bar_offset = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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(PCI_ROM_EXP_BAR_INDEX * 4) as u32
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} else {
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PCI_CONFIG_BAR_OFFSET + bar_id * 4
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};
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self.vfio_pci_configuration
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.write_config_dword(lsb_size, bar_offset);
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lsb_size = self.vfio_pci_configuration.read_config_dword(bar_offset);
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// We've just read the BAR size back. Or at least its LSB.
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let lsb_flag = lsb_size & PCI_CONFIG_MEMORY_BAR_FLAG_MASK;
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if lsb_size == 0 {
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bar_id += 1;
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continue;
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}
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// First read flags
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let flags = self.vfio_pci_configuration.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(lsb_flag & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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matches!(flags & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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} else {
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false
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};
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@ -851,7 +837,7 @@ impl PciDevice for VfioPciDevice {
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// Is this a 64-bit BAR?
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let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(
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lsb_flag & PCI_CONFIG_MEMORY_BAR_64BIT,
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flags & PCI_CONFIG_MEMORY_BAR_64BIT,
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PCI_CONFIG_MEMORY_BAR_64BIT
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)
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} else {
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@ -861,19 +847,31 @@ impl PciDevice for VfioPciDevice {
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// By default, the region type is 32 bits memory BAR.
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let mut region_type = PciBarRegionType::Memory32BitRegion;
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// To get size write all 1s
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self.vfio_pci_configuration
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.write_config_dword(0xffff_ffff, bar_offset);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = self.vfio_pci_configuration.read_config_dword(bar_offset);
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if io_bar {
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#[cfg(target_arch = "x86_64")]
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{
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// IO BAR
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region_type = PciBarRegionType::IoRegion;
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// Clear first bit.
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lsb_size &= 0xffff_fffc;
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// Mask flag bits (lowest 2 for I/O bars)
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lower &= !0b11;
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// BAR is not enabled
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert bits and add 1 to calculate size
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region_size = (!lower + 1) as u64;
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// Find the first bit that's set to 1.
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let first_bit = lsb_size.trailing_zeros();
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region_size = 2u64.pow(first_bit);
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// We need to allocate a guest PIO address range for that BAR.
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// The address needs to be 4 bytes aligned.
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bar_addr = allocator
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.allocate_io_addresses(None, region_size, Some(0x4))
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@ -881,43 +879,50 @@ impl PciDevice for VfioPciDevice {
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}
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#[cfg(target_arch = "aarch64")]
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unimplemented!()
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} else if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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self.vfio_pci_configuration
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.write_config_dword(0xffff_ffff, upper_offset);
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let upper = self.vfio_pci_configuration.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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// Mask out flag bits (lowest 4 for memory bars)
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combined_size &= !0b1111;
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// BAR is not enabled
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if combined_size == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!combined_size + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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} else {
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if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Mask out flag bits (lowest 4 for memory bars)
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lower &= !0b1111;
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msb_size = 0xffff_ffff;
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let msb_bar_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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self.vfio_pci_configuration
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.write_config_dword(msb_size, msb_bar_offset);
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msb_size = self
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.vfio_pci_configuration
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.read_config_dword(msb_bar_offset);
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Clear the first four bytes from our LSB.
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lsb_size &= 0xffff_fff0;
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// Invert and add 1 to to find size
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region_size = (!lower + 1) as u64;
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region_size = u64::from(msb_size);
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region_size <<= 32;
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region_size |= u64::from(lsb_size);
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// Find the first that's set to 1.
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let first_bit = region_size.trailing_zeros();
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region_size = 2u64.pow(first_bit);
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// BAR allocation needs to be naturally aligned
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if is_64bit_bar {
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bar_addr = allocator
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.allocate_mmio_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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} else {
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bar_addr = allocator
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.allocate_mmio_hole_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_hole_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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let reg_idx = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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@ -935,7 +940,7 @@ impl PciDevice for VfioPciDevice {
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if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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self.configuration
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.add_pci_rom_bar(&config, lsb_flag & 0x1)
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.add_pci_rom_bar(&config, flags & 0x1)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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} else {
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self.configuration
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