From 72b736153e09e3546c6d76cacd200342a3636848 Mon Sep 17 00:00:00 2001 From: Xie Yongji Date: Tue, 19 Jan 2021 17:17:53 +0800 Subject: [PATCH] vm-virtio: Fix update_avail_event() memory ordering We should use full memory barrier to ensure both guest and us can see the correct avail_idx and avail_event_idx. Something like this pattern: VM: CLH: update vring.avail->idx update avail_event_idx mb() mb() read avail_event_idx read vring.avail->idx Signed-off-by: Xie Yongji --- vm-virtio/src/queue.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vm-virtio/src/queue.rs b/vm-virtio/src/queue.rs index c4c7fb44d..e586b2bce 100644 --- a/vm-virtio/src/queue.rs +++ b/vm-virtio/src/queue.rs @@ -607,8 +607,8 @@ impl Queue { None => warn!("Can't update avail_event"), } - // This fence ensures the guest sees the value we've just written. - fence(Ordering::Release); + // This fence ensures both guest and us see the correct value (avail idx and avail event) + fence(Ordering::SeqCst); } /// Return the value present in the used_event field of the avail ring.