diff --git a/devices/src/legacy/gpio_pl061.rs b/devices/src/legacy/gpio_pl061.rs index 72ea05791..55d18c867 100644 --- a/devices/src/legacy/gpio_pl061.rs +++ b/devices/src/legacy/gpio_pl061.rs @@ -383,7 +383,7 @@ mod tests { // Read and write to the GPIODIR register. // Set pin 0 output pin. write_le_u32(&mut data, 1); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIODIR, &mut data); let v = read_le_u32(&data); assert_eq!(v, 1); @@ -391,8 +391,8 @@ mod tests { // Read and write to the GPIODATA register. write_le_u32(&mut data, 1); // Set pin 0 high. - let offset = 0x00000004 as u64; - gpio.write(LEGACY_GPIO_MAPPED_IO_START, offset, &mut data); + let offset = 0x00000004_u64; + gpio.write(LEGACY_GPIO_MAPPED_IO_START, offset, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, offset, &mut data); let v = read_le_u32(&data); assert_eq!(v, 1); @@ -400,7 +400,7 @@ mod tests { // Read and write to the GPIOIS register. // Configure pin 0 detecting level interrupt. write_le_u32(&mut data, 1); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIS, &mut data); let v = read_le_u32(&data); assert_eq!(v, 1); @@ -408,7 +408,7 @@ mod tests { // Read and write to the GPIOIBE register. // Configure pin 1 detecting both falling and rising edges. write_le_u32(&mut data, 2); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIBE, &mut data); let v = read_le_u32(&data); assert_eq!(v, 2); @@ -416,7 +416,7 @@ mod tests { // Read and write to the GPIOIEV register. // Configure pin 2 detecting both falling and rising edges. write_le_u32(&mut data, 4); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIEV, &mut data); let v = read_le_u32(&data); assert_eq!(v, 4); @@ -425,12 +425,12 @@ mod tests { // Configure pin 0...2 capable of triggering their individual interrupts // and then the combined GPIOINTR line. write_le_u32(&mut data, 7); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIE, &mut data); let v = read_le_u32(&data); assert_eq!(v, 7); - let mask = 0x00000002 as u32; + let mask = 0x00000002_u32; // emulate an rising pulse in pin 1. gpio.data |= !(gpio.data & mask) & mask; gpio.pl061_internal_update(); @@ -443,14 +443,14 @@ mod tests { // Read and Write to the GPIOIC register. // clear interrupt in pin 1. write_le_u32(&mut data, 2); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &data); gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIOIC, &mut data); let v = read_le_u32(&data); assert_eq!(v, 2); // Attempts to write beyond the writable space. write_le_u32(&mut data, 0); - gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &mut data); + gpio.write(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &data); let mut data = [0; 4]; gpio.read(LEGACY_GPIO_MAPPED_IO_START, GPIO_ID_LOW, &mut data); diff --git a/devices/src/legacy/rtc_pl031.rs b/devices/src/legacy/rtc_pl031.rs index 9d2f87b35..a6c0a63ce 100644 --- a/devices/src/legacy/rtc_pl031.rs +++ b/devices/src/legacy/rtc_pl031.rs @@ -457,7 +457,7 @@ mod tests { // Read and write to the MR register. write_le_u32(&mut data, 123); - rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCMR, &data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCMR, &mut data); let v = read_le_u32(&data); assert_eq!(v, 123); @@ -466,7 +466,7 @@ mod tests { let v = get_time(ClockType::Real); write_le_u32(&mut data, (v / NANOS_PER_SECOND) as u32); let previous_now_before = rtc.previous_now; - rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCLR, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCLR, &data); assert!(rtc.previous_now > previous_now_before); @@ -478,7 +478,7 @@ mod tests { // Test with non zero value. let non_zero = 1; write_le_u32(&mut data, non_zero); - rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &data); // The interrupt line should be on. assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() == 1); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); @@ -487,14 +487,14 @@ mod tests { // Now test with 0. write_le_u32(&mut data, 0); - rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCIMSC, &mut data); let v = read_le_u32(&data); assert_eq!(0, v); // Read and write to the ICR register. write_le_u32(&mut data, 1); - rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCICR, &data); // The interrupt line should be on. assert!(rtc.interrupt.notifier(0).unwrap().read().unwrap() > 1); let v_before = read_le_u32(&data); @@ -506,7 +506,7 @@ mod tests { // Attempts to turn off the RTC should not go through. write_le_u32(&mut data, 0); - rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, RTCCR, &data); rtc.read(LEGACY_RTC_MAPPED_IO_START, RTCCR, &mut data); let v = read_le_u32(&data); assert_eq!(v, 1); @@ -514,7 +514,7 @@ mod tests { // Attempts to write beyond the writable space. Using here the space used to read // the CID and PID from. write_le_u32(&mut data, 0); - rtc.write(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &mut data); + rtc.write(LEGACY_RTC_MAPPED_IO_START, AMBA_ID_LOW, &data); // However, reading from the AMBA_ID_LOW should succeed upon read. let mut data = [0; 4];