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https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-08-21 07:21:15 +00:00
pci, virtio-devices: Extend barrier returning through PCI code
We need to be able to return the barrier from the code that prepares to activate the virtio device. This triggered by a write to the configuration fields stored in the PCI BAR. Since bars can be accessed by both memory mapping and through PCI config I/O several prototypes must be changed. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
parent
a8643dc523
commit
7cc729c7d9
@ -71,8 +71,14 @@ impl PciRoot {
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impl BusDevice for PciRoot {}
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impl BusDevice for PciRoot {}
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impl PciDevice for PciRoot {
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impl PciDevice for PciRoot {
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fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
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fn write_config_register(
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&mut self,
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reg_idx: usize,
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offset: u64,
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data: &[u8],
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) -> Option<Arc<Barrier>> {
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self.config.write_config_register(reg_idx, offset, data);
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self.config.write_config_register(reg_idx, offset, data);
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None
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}
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}
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fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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@ -225,14 +231,14 @@ impl PciConfigIo {
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})
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})
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}
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}
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pub fn config_space_write(&mut self, offset: u64, data: &[u8]) {
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pub fn config_space_write(&mut self, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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if offset as usize + data.len() > 4 {
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if offset as usize + data.len() > 4 {
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return;
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return None;
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}
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}
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let enabled = (self.config_address & 0x8000_0000) != 0;
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let enabled = (self.config_address & 0x8000_0000) != 0;
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if !enabled {
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if !enabled {
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return;
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return None;
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}
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}
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let (bus, device, _function, register) =
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let (bus, device, _function, register) =
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@ -240,7 +246,7 @@ impl PciConfigIo {
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// Only support one bus.
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// Only support one bus.
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if bus != 0 {
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if bus != 0 {
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return;
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return None;
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}
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}
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let pci_bus = self.pci_bus.lock().unwrap();
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let pci_bus = self.pci_bus.lock().unwrap();
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@ -265,7 +271,9 @@ impl PciConfigIo {
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}
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}
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// Update the register value
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// Update the register value
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device.write_config_register(register, offset, data);
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device.write_config_register(register, offset, data)
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} else {
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None
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}
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}
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}
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}
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@ -315,12 +323,13 @@ impl BusDevice for PciConfigIo {
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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// `offset` is relative to 0xcf8
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// `offset` is relative to 0xcf8
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match offset {
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match offset {
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o @ 0..=3 => self.set_config_address(o, data),
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o @ 0..=3 => {
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self.set_config_address(o, data);
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None
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}
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o @ 4..=7 => self.config_space_write(o - 4, data),
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o @ 4..=7 => self.config_space_write(o - 4, data),
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_ => (),
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_ => None,
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};
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}
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None
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}
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}
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}
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}
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@ -5,6 +5,7 @@
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use crate::configuration::{self, PciBarRegionType};
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use crate::configuration::{self, PciBarRegionType};
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use std::any::Any;
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use std::any::Any;
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use std::fmt::{self, Display};
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use std::fmt::{self, Display};
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use std::sync::{Arc, Barrier};
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use std::{self, io, result};
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use std::{self, io, result};
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use vm_allocator::SystemAllocator;
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use vm_allocator::SystemAllocator;
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use vm_device::BusDevice;
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use vm_device::BusDevice;
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@ -63,7 +64,12 @@ pub trait PciDevice: BusDevice {
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/// Sets a register in the configuration space.
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/// Sets a register in the configuration space.
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/// * `reg_idx` - The index of the config register to modify.
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/// * `reg_idx` - The index of the config register to modify.
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/// * `offset` - Offset in to the register.
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/// * `offset` - Offset in to the register.
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fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]);
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fn write_config_register(
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&mut self,
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reg_idx: usize,
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offset: u64,
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data: &[u8],
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) -> Option<Arc<Barrier>>;
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/// Gets a register from the configuration space.
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/// Gets a register from the configuration space.
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/// * `reg_idx` - The index of the config register to read.
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/// * `reg_idx` - The index of the config register to read.
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fn read_config_register(&mut self, reg_idx: usize) -> u32;
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fn read_config_register(&mut self, reg_idx: usize) -> u32;
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@ -82,7 +88,9 @@ pub trait PciDevice: BusDevice {
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/// Writes to a BAR region mapped in to the device.
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/// Writes to a BAR region mapped in to the device.
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/// * `addr` - The guest address inside the BAR.
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/// * `addr` - The guest address inside the BAR.
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/// * `data` - The data to write.
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/// * `data` - The data to write.
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fn write_bar(&mut self, _base: u64, _offset: u64, _data: &[u8]) {}
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fn write_bar(&mut self, _base: u64, _offset: u64, _data: &[u8]) -> Option<Arc<Barrier>> {
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None
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}
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/// Relocates the BAR to a different address in guest address space.
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/// Relocates the BAR to a different address in guest address space.
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fn move_bar(&mut self, _old_base: u64, _new_base: u64) -> result::Result<(), io::Error> {
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fn move_bar(&mut self, _old_base: u64, _new_base: u64) -> result::Result<(), io::Error> {
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Ok(())
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Ok(())
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@ -653,9 +653,7 @@ impl BusDevice for VfioPciDevice {
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}
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}
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fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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self.write_bar(base, offset, data);
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self.write_bar(base, offset, data)
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None
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}
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}
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}
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}
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@ -885,7 +883,12 @@ impl PciDevice for VfioPciDevice {
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Ok(())
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Ok(())
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}
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}
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fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
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fn write_config_register(
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&mut self,
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reg_idx: usize,
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offset: u64,
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data: &[u8],
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) -> Option<Arc<Barrier>> {
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// When the guest wants to write to a BAR, we trap it into
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// When the guest wants to write to a BAR, we trap it into
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// our local configuration space. We're not reprogramming
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// our local configuration space. We're not reprogramming
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// VFIO device.
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// VFIO device.
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@ -895,9 +898,9 @@ impl PciDevice for VfioPciDevice {
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// We keep our local cache updated with the BARs.
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// We keep our local cache updated with the BARs.
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// We'll read it back from there when the guest is asking
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// We'll read it back from there when the guest is asking
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// for BARs (see read_config_register()).
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// for BARs (see read_config_register()).
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return self
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self.configuration
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.configuration
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.write_config_register(reg_idx, offset, data);
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.write_config_register(reg_idx, offset, data);
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return None;
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}
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}
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let reg = (reg_idx * PCI_CONFIG_REGISTER_SIZE) as u64;
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let reg = (reg_idx * PCI_CONFIG_REGISTER_SIZE) as u64;
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@ -933,6 +936,8 @@ impl PciDevice for VfioPciDevice {
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// to the device region to update the MSI Enable bit.
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// to the device region to update the MSI Enable bit.
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self.device
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self.device
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.region_write(VFIO_PCI_CONFIG_REGION_INDEX, data, reg + offset);
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.region_write(VFIO_PCI_CONFIG_REGION_INDEX, data, reg + offset);
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None
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}
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}
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fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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@ -990,7 +995,7 @@ impl PciDevice for VfioPciDevice {
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}
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}
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}
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}
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fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) {
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fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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let addr = base + offset;
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let addr = base + offset;
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if let Some(region) = self.find_region(addr) {
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if let Some(region) = self.find_region(addr) {
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let offset = addr - region.start.raw_value();
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let offset = addr - region.start.raw_value();
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@ -1002,6 +1007,8 @@ impl PciDevice for VfioPciDevice {
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self.device.region_write(region.index, data, offset);
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self.device.region_write(region.index, data, offset);
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}
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}
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}
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}
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None
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}
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}
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fn move_bar(&mut self, old_base: u64, new_base: u64) -> result::Result<(), io::Error> {
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fn move_bar(&mut self, old_base: u64, new_base: u64) -> result::Result<(), io::Error> {
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@ -617,18 +617,19 @@ impl VirtioPciDevice {
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}
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}
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}
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}
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fn write_cap_pci_cfg(&mut self, offset: usize, data: &[u8]) {
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fn write_cap_pci_cfg(&mut self, offset: usize, data: &[u8]) -> Option<Arc<Barrier>> {
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let cap_slice = self.cap_pci_cfg_info.cap.as_mut_slice();
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let cap_slice = self.cap_pci_cfg_info.cap.as_mut_slice();
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let data_len = data.len();
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let data_len = data.len();
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let cap_len = cap_slice.len();
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let cap_len = cap_slice.len();
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if offset + data_len > cap_len {
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if offset + data_len > cap_len {
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error!("Failed to write cap_pci_cfg to config space");
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error!("Failed to write cap_pci_cfg to config space");
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return;
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return None;
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}
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}
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if offset < std::mem::size_of::<VirtioPciCap>() {
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if offset < std::mem::size_of::<VirtioPciCap>() {
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let (_, right) = cap_slice.split_at_mut(offset);
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let (_, right) = cap_slice.split_at_mut(offset);
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right[..data_len].copy_from_slice(&data[..]);
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right[..data_len].copy_from_slice(&data[..]);
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None
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} else {
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} else {
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// Safe since we know self.cap_pci_cfg_info.cap.cap.offset is 32bits long.
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// Safe since we know self.cap_pci_cfg_info.cap.cap.offset is 32bits long.
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let bar_offset: u32 =
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let bar_offset: u32 =
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@ -733,7 +734,12 @@ impl VirtioInterrupt for VirtioInterruptMsix {
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}
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}
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impl PciDevice for VirtioPciDevice {
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impl PciDevice for VirtioPciDevice {
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fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
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fn write_config_register(
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&mut self,
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reg_idx: usize,
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offset: u64,
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data: &[u8],
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) -> Option<Arc<Barrier>> {
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// Handle the special case where the capability VIRTIO_PCI_CAP_PCI_CFG
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// Handle the special case where the capability VIRTIO_PCI_CAP_PCI_CFG
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// is accessed. This capability has a special meaning as it allows the
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// is accessed. This capability has a special meaning as it allows the
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// guest to access other capabilities without mapping the PCI BAR.
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// guest to access other capabilities without mapping the PCI BAR.
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@ -743,10 +749,11 @@ impl PciDevice for VirtioPciDevice {
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<= self.cap_pci_cfg_info.offset + self.cap_pci_cfg_info.cap.bytes().len()
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<= self.cap_pci_cfg_info.offset + self.cap_pci_cfg_info.cap.bytes().len()
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{
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{
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let offset = base + offset as usize - self.cap_pci_cfg_info.offset;
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let offset = base + offset as usize - self.cap_pci_cfg_info.offset;
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self.write_cap_pci_cfg(offset, data);
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self.write_cap_pci_cfg(offset, data)
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} else {
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} else {
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self.configuration
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self.configuration
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.write_config_register(reg_idx, offset, data);
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.write_config_register(reg_idx, offset, data);
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None
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}
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}
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}
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}
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@ -925,7 +932,7 @@ impl PciDevice for VirtioPciDevice {
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}
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}
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}
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}
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fn write_bar(&mut self, _base: u64, offset: u64, data: &[u8]) {
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fn write_bar(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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match offset {
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match offset {
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o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.write(
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o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.write(
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o - COMMON_CONFIG_BAR_OFFSET,
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o - COMMON_CONFIG_BAR_OFFSET,
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@ -1006,6 +1013,8 @@ impl PciDevice for VirtioPciDevice {
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self.common_config.driver_status = crate::DEVICE_FAILED as u8;
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self.common_config.driver_status = crate::DEVICE_FAILED as u8;
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}
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}
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}
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}
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None
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}
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}
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fn as_any(&mut self) -> &mut dyn Any {
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fn as_any(&mut self) -> &mut dyn Any {
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@ -1019,8 +1028,7 @@ impl BusDevice for VirtioPciDevice {
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}
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}
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fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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self.write_bar(base, offset, data);
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self.write_bar(base, offset, data)
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None
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}
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}
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}
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}
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