From 84bbaf06d1e3cacac9adae050fbbd4ddaadaac7c Mon Sep 17 00:00:00 2001 From: Wei Liu Date: Fri, 8 Jul 2022 14:08:10 +0000 Subject: [PATCH] hypervisor: turn boot_msr_entries into a trait method This allows dispatching to either KVM or MSHV automatically. No functional change. Signed-off-by: Wei Liu --- arch/src/x86_64/regs.rs | 2 +- hypervisor/src/cpu.rs | 5 +++++ hypervisor/src/kvm/mod.rs | 26 ++++++++++++++++++++++++++ hypervisor/src/kvm/x86_64/mod.rs | 22 +--------------------- hypervisor/src/mshv/mod.rs | 21 +++++++++++++++++++++ hypervisor/src/mshv/x86_64/mod.rs | 18 +----------------- vmm/src/cpu.rs | 2 +- 7 files changed, 56 insertions(+), 40 deletions(-) diff --git a/arch/src/x86_64/regs.rs b/arch/src/x86_64/regs.rs index 7b4c990e3..6df184200 100644 --- a/arch/src/x86_64/regs.rs +++ b/arch/src/x86_64/regs.rs @@ -66,7 +66,7 @@ pub fn setup_fpu(vcpu: &Arc) -> Result<()> { /// /// * `vcpu` - Structure for the VCPU that holds the VCPU's fd. pub fn setup_msrs(vcpu: &Arc) -> Result<()> { - vcpu.set_msrs(&hypervisor::x86_64::boot_msr_entries()) + vcpu.set_msrs(&vcpu.boot_msr_entries()) .map_err(Error::SetModelSpecificRegisters)?; Ok(()) diff --git a/hypervisor/src/cpu.rs b/hypervisor/src/cpu.rs index e5c275f3a..4d31b9e69 100644 --- a/hypervisor/src/cpu.rs +++ b/hypervisor/src/cpu.rs @@ -501,4 +501,9 @@ pub trait Vcpu: Send + Sync { /// Set the status code for TDX exit /// fn set_tdx_status(&mut self, status: TdxExitStatus); + #[cfg(target_arch = "x86_64")] + /// + /// Return the list of initial MSR entries for a VCPU + /// + fn boot_msr_entries(&self) -> MsrEntries; } diff --git a/hypervisor/src/kvm/mod.rs b/hypervisor/src/kvm/mod.rs index 07d486856..c7ae516dd 100644 --- a/hypervisor/src/kvm/mod.rs +++ b/hypervisor/src/kvm/mod.rs @@ -1905,6 +1905,32 @@ impl cpu::Vcpu for KvmVcpu { TdxExitStatus::InvalidOperand => TDG_VP_VMCALL_INVALID_OPERAND, }; } + #[cfg(target_arch = "x86_64")] + /// + /// Return the list of initial MSR entries for a VCPU + /// + fn boot_msr_entries(&self) -> MsrEntries { + use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; + use kvm_bindings::kvm_msr_entry as MsrEntry; + + MsrEntries::from_entries(&[ + msr!(msr_index::MSR_IA32_SYSENTER_CS), + msr!(msr_index::MSR_IA32_SYSENTER_ESP), + msr!(msr_index::MSR_IA32_SYSENTER_EIP), + msr!(msr_index::MSR_STAR), + msr!(msr_index::MSR_CSTAR), + msr!(msr_index::MSR_LSTAR), + msr!(msr_index::MSR_KERNEL_GS_BASE), + msr!(msr_index::MSR_SYSCALL_MASK), + msr!(msr_index::MSR_IA32_TSC), + msr_data!( + msr_index::MSR_IA32_MISC_ENABLE, + msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64 + ), + msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), + ]) + .unwrap() + } } /// Device struct for KVM diff --git a/hypervisor/src/kvm/x86_64/mod.rs b/hypervisor/src/kvm/x86_64/mod.rs index 4a1c6c8bb..b05f474a7 100644 --- a/hypervisor/src/kvm/x86_64/mod.rs +++ b/hypervisor/src/kvm/x86_64/mod.rs @@ -8,7 +8,7 @@ // // -use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; +use crate::arch::x86::SegmentRegisterOps; use crate::kvm::{Cap, Kvm, KvmError, KvmResult}; use serde::{Deserialize, Serialize}; @@ -91,26 +91,6 @@ impl SegmentRegisterOps for SegmentRegister { } } -pub fn boot_msr_entries() -> MsrEntries { - MsrEntries::from_entries(&[ - msr!(msr_index::MSR_IA32_SYSENTER_CS), - msr!(msr_index::MSR_IA32_SYSENTER_ESP), - msr!(msr_index::MSR_IA32_SYSENTER_EIP), - msr!(msr_index::MSR_STAR), - msr!(msr_index::MSR_CSTAR), - msr!(msr_index::MSR_LSTAR), - msr!(msr_index::MSR_KERNEL_GS_BASE), - msr!(msr_index::MSR_SYSCALL_MASK), - msr!(msr_index::MSR_IA32_TSC), - msr_data!( - msr_index::MSR_IA32_MISC_ENABLE, - msr_index::MSR_IA32_MISC_ENABLE_FAST_STRING as u64 - ), - msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), - ]) - .unwrap() -} - /// /// Check KVM extension for Linux /// diff --git a/hypervisor/src/mshv/mod.rs b/hypervisor/src/mshv/mod.rs index d28bb8b80..086305f5c 100644 --- a/hypervisor/src/mshv/mod.rs +++ b/hypervisor/src/mshv/mod.rs @@ -593,6 +593,27 @@ impl cpu::Vcpu for MshvVcpu { .get_suspend_regs() .map_err(|e| cpu::HypervisorCpuError::GetSuspendRegs(e.into())) } + #[cfg(target_arch = "x86_64")] + /// + /// Return the list of initial MSR entries for a VCPU + /// + fn boot_msr_entries(&self) -> MsrEntries { + use crate::arch::x86::{msr_index, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; + + MsrEntries::from_entries(&[ + msr!(msr_index::MSR_IA32_SYSENTER_CS), + msr!(msr_index::MSR_IA32_SYSENTER_ESP), + msr!(msr_index::MSR_IA32_SYSENTER_EIP), + msr!(msr_index::MSR_STAR), + msr!(msr_index::MSR_CSTAR), + msr!(msr_index::MSR_LSTAR), + msr!(msr_index::MSR_KERNEL_GS_BASE), + msr!(msr_index::MSR_SYSCALL_MASK), + msr!(msr_index::MSR_IA32_TSC), + msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), + ]) + .unwrap() + } } /// Device struct for MSHV diff --git a/hypervisor/src/mshv/x86_64/mod.rs b/hypervisor/src/mshv/x86_64/mod.rs index 16d8191de..04bad672a 100644 --- a/hypervisor/src/mshv/x86_64/mod.rs +++ b/hypervisor/src/mshv/x86_64/mod.rs @@ -7,7 +7,7 @@ // Copyright 2018-2019 CrowdStrike, Inc. // // -use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; +use crate::arch::x86::SegmentRegisterOps; use serde::{Deserialize, Serialize}; use std::fmt; @@ -134,19 +134,3 @@ impl SegmentRegisterOps for SegmentRegister { self.db = val; } } - -pub fn boot_msr_entries() -> MsrEntries { - MsrEntries::from_entries(&[ - msr!(msr_index::MSR_IA32_SYSENTER_CS), - msr!(msr_index::MSR_IA32_SYSENTER_ESP), - msr!(msr_index::MSR_IA32_SYSENTER_EIP), - msr!(msr_index::MSR_STAR), - msr!(msr_index::MSR_CSTAR), - msr!(msr_index::MSR_LSTAR), - msr!(msr_index::MSR_KERNEL_GS_BASE), - msr!(msr_index::MSR_SYSCALL_MASK), - msr!(msr_index::MSR_IA32_TSC), - msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), - ]) - .unwrap() -} diff --git a/vmm/src/cpu.rs b/vmm/src/cpu.rs index c8595f12a..fce0cd576 100644 --- a/vmm/src/cpu.rs +++ b/vmm/src/cpu.rs @@ -2412,7 +2412,7 @@ mod tests { // Official entries that were setup when we did setup_msrs. We need to assert that the // tenth one (i.e the one with index msr_index::MSR_IA32_MISC_ENABLE has the data we // expect. - let entry_vec = hypervisor::x86_64::boot_msr_entries(); + let entry_vec = vcpu.boot_msr_entries(); assert_eq!(entry_vec.as_slice()[9], msrs.as_slice()[0]); }