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hypervisor: mshv: Reduce msrs visibility to x86_64
Model Specific Registers (MSRs) are usually available on x86 architecture. So, let's reduce the visibility of MSRs to just x86 architecture. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
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dd37f33a43
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@ -290,27 +290,39 @@ impl hypervisor::Hypervisor for MshvHypervisor {
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)
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.map_err(|e| hypervisor::HypervisorError::SetPartitionProperty(e.into()))?;
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let msr_list = self.get_msr_list()?;
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let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
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let mut msrs: Vec<MsrEntry> = vec![
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MsrEntry {
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..Default::default()
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};
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num_msrs
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];
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let indices = msr_list.as_slice();
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for (pos, index) in indices.iter().enumerate() {
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msrs[pos].index = *index;
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}
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let vm_fd = Arc::new(fd);
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Ok(Arc::new(MshvVm {
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fd: vm_fd,
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msrs,
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dirty_log_slots: Arc::new(RwLock::new(HashMap::new())),
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#[cfg(feature = "sev_snp")]
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sev_snp_enabled: mshv_vm_type == VmType::Snp,
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}))
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#[cfg(target_arch = "x86_64")]
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{
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let msr_list = self.get_msr_list()?;
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let num_msrs = msr_list.as_fam_struct_ref().nmsrs as usize;
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let mut msrs: Vec<MsrEntry> = vec![
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MsrEntry {
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..Default::default()
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};
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num_msrs
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];
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let indices = msr_list.as_slice();
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for (pos, index) in indices.iter().enumerate() {
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msrs[pos].index = *index;
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}
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Ok(Arc::new(MshvVm {
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fd: vm_fd,
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msrs,
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dirty_log_slots: Arc::new(RwLock::new(HashMap::new())),
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#[cfg(feature = "sev_snp")]
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sev_snp_enabled: mshv_vm_type == VmType::Snp,
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}))
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}
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#[cfg(target_arch = "aarch64")]
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{
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Ok(Arc::new(MshvVm {
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fd: vm_fd,
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dirty_log_slots: Arc::new(RwLock::new(HashMap::new())),
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}))
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}
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}
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/// Create a mshv vm object and return the object as Vm trait object
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@ -1538,6 +1550,7 @@ impl<'a> PlatformEmulator for MshvEmulatorContext<'a> {
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/// Wrapper over Mshv VM ioctls.
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pub struct MshvVm {
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fd: Arc<VmFd>,
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#[cfg(target_arch = "x86_64")]
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msrs: Vec<MsrEntry>,
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dirty_log_slots: Arc<RwLock<HashMap<u64, MshvDirtyLogSlot>>>,
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#[cfg(feature = "sev_snp")]
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