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resources: kernel: Enable 5 levels of page table
Some CPUs might support up to 52 bits of addressable space, that's the reason why we need the guest kernel to support 5 levels of page table. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
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@ -286,7 +286,7 @@ CONFIG_X86_64_SMP=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_DYNAMIC_PHYSICAL_MASK=y
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CONFIG_PGTABLE_LEVELS=4
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CONFIG_PGTABLE_LEVELS=5
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CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
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#
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@ -371,7 +371,7 @@ CONFIG_X86_VSYSCALL_EMULATION=y
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# CONFIG_MICROCODE is not set
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CONFIG_X86_MSR=y
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CONFIG_X86_CPUID=y
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# CONFIG_X86_5LEVEL is not set
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CONFIG_X86_5LEVEL=y
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CONFIG_X86_DIRECT_GBPAGES=y
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# CONFIG_X86_CPA_STATISTICS is not set
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CONFIG_AMD_MEM_ENCRYPT=y
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