resources: kernel: Enable 5 levels of page table

Some CPUs might support up to 52 bits of addressable space, that's the
reason why we need the guest kernel to support 5 levels of page table.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2020-06-09 17:04:13 +02:00 committed by Rob Bradford
parent 653087d7a3
commit 96a5e22bd6

View File

@ -286,7 +286,7 @@ CONFIG_X86_64_SMP=y
CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y CONFIG_FIX_EARLYCON_MEM=y
CONFIG_DYNAMIC_PHYSICAL_MASK=y CONFIG_DYNAMIC_PHYSICAL_MASK=y
CONFIG_PGTABLE_LEVELS=4 CONFIG_PGTABLE_LEVELS=5
CONFIG_CC_HAS_SANE_STACKPROTECTOR=y CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
# #
@ -371,7 +371,7 @@ CONFIG_X86_VSYSCALL_EMULATION=y
# CONFIG_MICROCODE is not set # CONFIG_MICROCODE is not set
CONFIG_X86_MSR=y CONFIG_X86_MSR=y
CONFIG_X86_CPUID=y CONFIG_X86_CPUID=y
# CONFIG_X86_5LEVEL is not set CONFIG_X86_5LEVEL=y
CONFIG_X86_DIRECT_GBPAGES=y CONFIG_X86_DIRECT_GBPAGES=y
# CONFIG_X86_CPA_STATISTICS is not set # CONFIG_X86_CPA_STATISTICS is not set
CONFIG_AMD_MEM_ENCRYPT=y CONFIG_AMD_MEM_ENCRYPT=y