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https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-10-02 11:35:46 +00:00
vmm, arch: Move max_phys_bits handling to shared CPUID code
Move the code for populating the CPUID with details of the maximum address space from the per-vCPU CPUID handling code to the shared CPUID handling code. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
parent
48963e322a
commit
9792c9aafa
@ -63,7 +63,6 @@ pub fn configure_vcpu(
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id: u8,
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id: u8,
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kernel_entry_point: Option<EntryPoint>,
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kernel_entry_point: Option<EntryPoint>,
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vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
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vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
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_phys_bits: u8,
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) -> super::Result<u64> {
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) -> super::Result<u64> {
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if let Some(kernel_entry_point) = kernel_entry_point {
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if let Some(kernel_entry_point) = kernel_entry_point {
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regs::setup_regs(
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regs::setup_regs(
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@ -336,7 +336,6 @@ pub fn configure_vcpu(
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vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
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vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
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cpuid: CpuId,
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cpuid: CpuId,
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kvm_hyperv: bool,
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kvm_hyperv: bool,
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phys_bits: u8,
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) -> super::Result<()> {
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) -> super::Result<()> {
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let mut cpuid = cpuid;
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let mut cpuid = cpuid;
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CpuidPatch::set_cpuid_reg(&mut cpuid, 0xb, None, CpuidReg::EDX, u32::from(id));
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CpuidPatch::set_cpuid_reg(&mut cpuid, 0xb, None, CpuidReg::EDX, u32::from(id));
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@ -410,13 +409,6 @@ pub fn configure_vcpu(
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.map_err(|_| Error::PopulatingCpuid)?;
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.map_err(|_| Error::PopulatingCpuid)?;
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}
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}
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// Set CPU physical bits
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for entry in cpuid.as_mut_slice().iter_mut() {
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if entry.function == 0x8000_0008 {
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entry.eax = (entry.eax & 0xffff_ff00) | (phys_bits as u32 & 0xff);
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}
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}
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fd.set_cpuid2(&cpuid)
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fd.set_cpuid2(&cpuid)
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.map_err(|e| Error::SetSupportedCpusFailed(e.into()))?;
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.map_err(|e| Error::SetSupportedCpusFailed(e.into()))?;
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@ -17,6 +17,7 @@ use crate::config::CpusConfig;
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use crate::device_manager::DeviceManager;
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use crate::device_manager::DeviceManager;
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use crate::memory_manager::MemoryManager;
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use crate::memory_manager::MemoryManager;
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use crate::seccomp_filters::{get_seccomp_filter, Thread};
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use crate::seccomp_filters::{get_seccomp_filter, Thread};
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#[cfg(target_arch = "x86_64")]
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use crate::vm::physical_bits;
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use crate::vm::physical_bits;
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use crate::CPU_MANAGER_SNAPSHOT_ID;
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use crate::CPU_MANAGER_SNAPSHOT_ID;
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#[cfg(feature = "acpi")]
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#[cfg(feature = "acpi")]
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@ -258,19 +259,12 @@ impl Vcpu {
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vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
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vm_memory: &GuestMemoryAtomic<GuestMemoryMmap>,
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#[cfg(target_arch = "x86_64")] cpuid: CpuId,
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#[cfg(target_arch = "x86_64")] cpuid: CpuId,
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#[cfg(target_arch = "x86_64")] kvm_hyperv: bool,
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#[cfg(target_arch = "x86_64")] kvm_hyperv: bool,
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phys_bits: u8,
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) -> Result<()> {
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) -> Result<()> {
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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{
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{
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self.init(vm)?;
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self.init(vm)?;
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self.mpidr = arch::configure_vcpu(
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self.mpidr = arch::configure_vcpu(&self.vcpu, self.id, kernel_entry_point, vm_memory)
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&self.vcpu,
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.map_err(Error::VcpuConfiguration)?;
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self.id,
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kernel_entry_point,
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vm_memory,
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phys_bits,
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)
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.map_err(Error::VcpuConfiguration)?;
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}
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}
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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@ -281,7 +275,6 @@ impl Vcpu {
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vm_memory,
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vm_memory,
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cpuid,
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cpuid,
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kvm_hyperv,
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kvm_hyperv,
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phys_bits,
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)
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)
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.map_err(Error::VcpuConfiguration)?;
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.map_err(Error::VcpuConfiguration)?;
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@ -559,7 +552,10 @@ impl CpuManager {
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None
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None
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};
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};
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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let cpuid = CpuManager::patch_cpuid(hypervisor, &config.topology, sgx_epc_sections)?;
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let cpuid = {
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let phys_bits = physical_bits(config.max_phys_bits);
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CpuManager::patch_cpuid(hypervisor, &config.topology, sgx_epc_sections, phys_bits)?
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};
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let device_manager = device_manager.lock().unwrap();
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let device_manager = device_manager.lock().unwrap();
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#[cfg(feature = "acpi")]
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#[cfg(feature = "acpi")]
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@ -607,6 +603,7 @@ impl CpuManager {
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hypervisor: Arc<dyn hypervisor::Hypervisor>,
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hypervisor: Arc<dyn hypervisor::Hypervisor>,
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topology: &Option<CpuTopology>,
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topology: &Option<CpuTopology>,
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sgx_epc_sections: Option<Vec<SgxEpcSection>>,
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sgx_epc_sections: Option<Vec<SgxEpcSection>>,
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phys_bits: u8,
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) -> Result<CpuId> {
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) -> Result<CpuId> {
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let mut cpuid_patches = Vec::new();
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let mut cpuid_patches = Vec::new();
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@ -663,6 +660,13 @@ impl CpuManager {
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arch::x86_64::update_cpuid_sgx(&mut cpuid, sgx_epc_sections).unwrap();
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arch::x86_64::update_cpuid_sgx(&mut cpuid, sgx_epc_sections).unwrap();
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}
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}
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// Set CPU physical bits
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for entry in cpuid.as_mut_slice().iter_mut() {
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if entry.function == 0x8000_0008 {
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entry.eax = (entry.eax & 0xffff_ff00) | (phys_bits as u32 & 0xff);
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}
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}
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Ok(cpuid)
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Ok(cpuid)
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}
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}
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@ -688,8 +692,6 @@ impl CpuManager {
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} else {
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} else {
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let vm_memory = self.vm_memory.clone();
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let vm_memory = self.vm_memory.clone();
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let phys_bits = physical_bits(self.config.max_phys_bits);
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#[cfg(target_arch = "x86_64")]
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#[cfg(target_arch = "x86_64")]
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vcpu.lock()
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vcpu.lock()
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.unwrap()
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.unwrap()
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@ -698,14 +700,13 @@ impl CpuManager {
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&vm_memory,
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&vm_memory,
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self.cpuid.clone(),
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self.cpuid.clone(),
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self.config.kvm_hyperv,
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self.config.kvm_hyperv,
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phys_bits,
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)
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)
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.expect("Failed to configure vCPU");
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.expect("Failed to configure vCPU");
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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vcpu.lock()
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vcpu.lock()
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.unwrap()
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.unwrap()
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.configure(&self.vm, entry_point, &vm_memory, phys_bits)
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.configure(&self.vm, entry_point, &vm_memory)
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.expect("Failed to configure vCPU");
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.expect("Failed to configure vCPU");
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}
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}
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