mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-12-31 10:05:20 +00:00
vmm: cpu: Port CpuManager to Aml::append_aml_bytes()
Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford
parent
a7786b4e0c
commit
986e43f899
303
vmm/src/cpu.rs
303
vmm/src/cpu.rs
@ -1253,7 +1253,7 @@ impl Cpu {
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#[cfg(feature = "acpi")]
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impl Aml for Cpu {
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fn to_aml_bytes(&self) -> Vec<u8> {
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fn append_aml_bytes(&self, bytes: &mut Vec<u8>) {
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#[cfg(target_arch = "x86_64")]
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let mat_data: Vec<u8> = self.generate_mat();
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@ -1305,7 +1305,7 @@ impl Aml for Cpu {
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),
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],
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)
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.to_aml_bytes()
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.append_aml_bytes(bytes)
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}
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}
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@ -1316,13 +1316,13 @@ struct CpuNotify {
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#[cfg(feature = "acpi")]
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impl Aml for CpuNotify {
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fn to_aml_bytes(&self) -> Vec<u8> {
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fn append_aml_bytes(&self, bytes: &mut Vec<u8>) {
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let object = aml::Path::new(&format!("C{:03}", self.cpu_id));
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aml::If::new(
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&aml::Equal::new(&aml::Arg(0), &self.cpu_id),
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vec![&aml::Notify::new(&object, &aml::Arg(1))],
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)
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.to_aml_bytes()
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.append_aml_bytes(bytes)
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}
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}
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@ -1333,33 +1333,30 @@ struct CpuMethods {
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#[cfg(feature = "acpi")]
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impl Aml for CpuMethods {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let mut bytes = Vec::new();
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bytes.extend_from_slice(
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// CPU status method
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&aml::Method::new(
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"CSTA".into(),
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1,
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true,
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vec![
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// Take lock defined above
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xffff),
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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&aml::Store::new(&aml::Local(0), &aml::ZERO),
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// Check if CPEN bit is set, if so make the local variable 0xf (see _STA for details of meaning)
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CPEN"), &aml::ONE),
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vec![&aml::Store::new(&aml::Local(0), &0xfu8)],
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),
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// Release lock
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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// Return 0 or 0xf
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&aml::Return::new(&aml::Local(0)),
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],
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)
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.to_aml_bytes(),
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);
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fn append_aml_bytes(&self, bytes: &mut Vec<u8>) {
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// CPU status method
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aml::Method::new(
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"CSTA".into(),
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1,
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true,
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vec![
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// Take lock defined above
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xffff),
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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&aml::Store::new(&aml::Local(0), &aml::ZERO),
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// Check if CPEN bit is set, if so make the local variable 0xf (see _STA for details of meaning)
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CPEN"), &aml::ONE),
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vec![&aml::Store::new(&aml::Local(0), &0xfu8)],
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),
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// Release lock
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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// Return 0 or 0xf
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&aml::Return::new(&aml::Local(0)),
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],
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)
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.append_aml_bytes(bytes);
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let mut cpu_notifies = Vec::new();
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for cpu_id in 0..self.max_vcpus {
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@ -1371,144 +1368,125 @@ impl Aml for CpuMethods {
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cpu_notifies_refs.push(&cpu_notifies[usize::from(cpu_id)]);
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}
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bytes.extend_from_slice(
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&aml::Method::new("CTFY".into(), 2, true, cpu_notifies_refs).to_aml_bytes(),
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);
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aml::Method::new("CTFY".into(), 2, true, cpu_notifies_refs).append_aml_bytes(bytes);
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bytes.extend_from_slice(
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&aml::Method::new(
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"CEJ0".into(),
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1,
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true,
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vec![
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xffff),
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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// Set CEJ0 bit
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CEJ0"), &aml::ONE),
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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],
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)
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.to_aml_bytes(),
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);
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aml::Method::new(
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"CEJ0".into(),
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1,
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true,
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vec![
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xffff),
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Arg(0)),
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// Set CEJ0 bit
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CEJ0"), &aml::ONE),
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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],
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)
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.append_aml_bytes(bytes);
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bytes.extend_from_slice(
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&aml::Method::new(
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"CSCN".into(),
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0,
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true,
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vec![
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// Take lock defined above
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xffff),
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&aml::Store::new(&aml::Local(0), &aml::ZERO),
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&aml::While::new(
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&aml::LessThan::new(&aml::Local(0), &self.max_vcpus),
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vec![
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Local(0)),
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// Check if CINS bit is set
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CINS"), &aml::ONE),
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// Notify device if it is
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vec![
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&aml::MethodCall::new(
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"CTFY".into(),
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vec![&aml::Local(0), &aml::ONE],
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),
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// Reset CINS bit
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&aml::Store::new(
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&aml::Path::new("\\_SB_.PRES.CINS"),
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&aml::ONE,
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),
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],
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),
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// Check if CRMV bit is set
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CRMV"), &aml::ONE),
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// Notify device if it is (with the eject constant 0x3)
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vec![
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&aml::MethodCall::new(
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"CTFY".into(),
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vec![&aml::Local(0), &3u8],
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),
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// Reset CRMV bit
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&aml::Store::new(
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&aml::Path::new("\\_SB_.PRES.CRMV"),
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&aml::ONE,
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),
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],
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),
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&aml::Add::new(&aml::Local(0), &aml::Local(0), &aml::ONE),
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],
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),
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// Release lock
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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],
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)
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.to_aml_bytes(),
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);
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bytes
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aml::Method::new(
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"CSCN".into(),
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0,
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true,
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vec![
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// Take lock defined above
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&aml::Acquire::new("\\_SB_.PRES.CPLK".into(), 0xffff),
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&aml::Store::new(&aml::Local(0), &aml::ZERO),
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&aml::While::new(
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&aml::LessThan::new(&aml::Local(0), &self.max_vcpus),
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vec![
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// Write CPU number (in first argument) to I/O port via field
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CSEL"), &aml::Local(0)),
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// Check if CINS bit is set
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CINS"), &aml::ONE),
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// Notify device if it is
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vec![
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&aml::MethodCall::new(
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"CTFY".into(),
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vec![&aml::Local(0), &aml::ONE],
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),
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// Reset CINS bit
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CINS"), &aml::ONE),
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],
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),
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// Check if CRMV bit is set
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&aml::If::new(
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&aml::Equal::new(&aml::Path::new("\\_SB_.PRES.CRMV"), &aml::ONE),
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// Notify device if it is (with the eject constant 0x3)
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vec![
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&aml::MethodCall::new("CTFY".into(), vec![&aml::Local(0), &3u8]),
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// Reset CRMV bit
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&aml::Store::new(&aml::Path::new("\\_SB_.PRES.CRMV"), &aml::ONE),
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],
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),
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&aml::Add::new(&aml::Local(0), &aml::Local(0), &aml::ONE),
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],
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),
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// Release lock
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&aml::Release::new("\\_SB_.PRES.CPLK".into()),
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],
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)
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.append_aml_bytes(bytes)
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}
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}
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#[cfg(feature = "acpi")]
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impl Aml for CpuManager {
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fn to_aml_bytes(&self) -> Vec<u8> {
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let mut bytes = Vec::new();
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fn append_aml_bytes(&self, bytes: &mut Vec<u8>) {
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// CPU hotplug controller
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#[cfg(target_arch = "x86_64")]
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bytes.extend_from_slice(
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&aml::Device::new(
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"_SB_.PRES".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EisaName::new("PNP0A06")),
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&aml::Name::new("_UID".into(), &"CPU Hotplug Controller"),
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// Mutex to protect concurrent access as we write to choose CPU and then read back status
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&aml::Mutex::new("CPLK".into(), 0),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.acpi_address.0 as u64,
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self.acpi_address.0 + CPU_MANAGER_ACPI_SIZE as u64 - 1,
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)]),
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),
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// OpRegion and Fields map MMIO range into individual field values
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&aml::OpRegion::new(
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"PRST".into(),
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aml::OpRegionSpace::SystemMemory,
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self.acpi_address.0 as usize,
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CPU_MANAGER_ACPI_SIZE,
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),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::Byte,
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aml::FieldUpdateRule::WriteAsZeroes,
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vec![
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aml::FieldEntry::Reserved(32),
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aml::FieldEntry::Named(*b"CPEN", 1),
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aml::FieldEntry::Named(*b"CINS", 1),
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aml::FieldEntry::Named(*b"CRMV", 1),
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aml::FieldEntry::Named(*b"CEJ0", 1),
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aml::FieldEntry::Reserved(4),
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aml::FieldEntry::Named(*b"CCMD", 8),
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],
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),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::DWord,
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aml::FieldUpdateRule::Preserve,
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vec![
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aml::FieldEntry::Named(*b"CSEL", 32),
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aml::FieldEntry::Reserved(32),
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aml::FieldEntry::Named(*b"CDAT", 32),
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],
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),
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],
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)
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.to_aml_bytes(),
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);
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aml::Device::new(
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"_SB_.PRES".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EisaName::new("PNP0A06")),
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&aml::Name::new("_UID".into(), &"CPU Hotplug Controller"),
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// Mutex to protect concurrent access as we write to choose CPU and then read back status
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&aml::Mutex::new("CPLK".into(), 0),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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self.acpi_address.0 as u64,
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self.acpi_address.0 + CPU_MANAGER_ACPI_SIZE as u64 - 1,
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)]),
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),
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// OpRegion and Fields map MMIO range into individual field values
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&aml::OpRegion::new(
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"PRST".into(),
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aml::OpRegionSpace::SystemMemory,
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self.acpi_address.0 as usize,
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CPU_MANAGER_ACPI_SIZE,
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),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::Byte,
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aml::FieldUpdateRule::WriteAsZeroes,
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vec![
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aml::FieldEntry::Reserved(32),
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aml::FieldEntry::Named(*b"CPEN", 1),
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aml::FieldEntry::Named(*b"CINS", 1),
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aml::FieldEntry::Named(*b"CRMV", 1),
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aml::FieldEntry::Named(*b"CEJ0", 1),
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aml::FieldEntry::Reserved(4),
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aml::FieldEntry::Named(*b"CCMD", 8),
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],
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),
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&aml::Field::new(
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"PRST".into(),
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aml::FieldAccessType::DWord,
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aml::FieldUpdateRule::Preserve,
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vec![
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aml::FieldEntry::Named(*b"CSEL", 32),
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aml::FieldEntry::Reserved(32),
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aml::FieldEntry::Named(*b"CDAT", 32),
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],
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),
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],
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)
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.append_aml_bytes(bytes);
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// CPU devices
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let hid = aml::Name::new("_HID".into(), &"ACPI0010");
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@ -1534,10 +1512,7 @@ impl Aml for CpuManager {
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cpu_data_inner.push(cpu_device);
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}
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bytes.extend_from_slice(
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&aml::Device::new("_SB_.CPUS".into(), cpu_data_inner).to_aml_bytes(),
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);
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bytes
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aml::Device::new("_SB_.CPUS".into(), cpu_data_inner).append_aml_bytes(bytes)
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}
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}
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