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hypervisor: Support enabling HyperV synthetic interrupt controller

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This adds a KVM HyperV synthetic interrupt controller in place of the
emulated PIC.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford 2020-09-15 16:15:50 +01:00
parent 5495ab7415
commit 9b48ee38cb
2 changed files with 22 additions and 1 deletions
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10
hypervisor/src/cpu.rs
View File

@ -148,6 +148,11 @@ pub enum HypervisorCpuError {
///
#[error("Failed to notify guest its clock was paused: {0}")]
NotifyGuestClockPaused(#[source] anyhow::Error),
///
/// Enabling HyperV SynIC error
///
#[error("Failed to enable HyperV SynIC")]
EnableHyperVSynIC(#[source] anyhow::Error),
}
#[derive(Debug)]
@ -210,6 +215,11 @@ pub trait Vcpu: Send + Sync {
fn set_cpuid2(&self, cpuid: &CpuId) -> Result<()>;
#[cfg(target_arch = "x86_64")]
///
/// X86 specific call to enable HyperV SynIC
///
fn enable_hyperv_synic(&self) -> Result<()>;
#[cfg(target_arch = "x86_64")]
///
/// X86 specific call to retrieve the CPUID registers.
///
fn get_cpuid2(&self, num_entries: usize) -> Result<CpuId>;

13
hypervisor/src/kvm/mod.rs
View File

@ -38,7 +38,7 @@ pub use x86_64::{
};
#[cfg(target_arch = "x86_64")]
use kvm_bindings::{kvm_enable_cap, MsrList, KVM_CAP_SPLIT_IRQCHIP};
use kvm_bindings::{kvm_enable_cap, MsrList, KVM_CAP_HYPERV_SYNIC, KVM_CAP_SPLIT_IRQCHIP};
#[cfg(target_arch = "x86_64")]
use crate::arch::x86::NUM_IOAPIC_PINS;
@ -550,6 +550,17 @@ impl cpu::Vcpu for KvmVcpu {
.set_cpuid2(cpuid)
.map_err(|e| cpu::HypervisorCpuError::SetCpuid(e.into()))
}
#[cfg(target_arch = "x86_64")]
///
/// X86 specific call to enable HyperV SynIC
///
fn enable_hyperv_synic(&self) -> cpu::Result<()> {
let mut cap: kvm_enable_cap = Default::default();
cap.cap = KVM_CAP_HYPERV_SYNIC;
self.fd
.enable_cap(&cap)
.map_err(|e| cpu::HypervisorCpuError::EnableHyperVSynIC(e.into()))
}
///
/// X86 specific call to retrieve the CPUID registers.
///