misc: Manual beta clippy fixes (boolean to int conversion using if)

Signed-off-by: Rob Bradford <robert.bradford@intel.com>

hypervisor/src/arch/x86/emulator/instructions/cmp.rs

@@ -38,11 +38,7 @@ fn calc_rflags_cpazso(op0: u64, op1: u64, op_size: usize) -> u64 {
     // AF cares about the lowest 4 bits (nibble). msb_shift is 3 in this case.
     let af = ((cout >> 3) & 0x1) << AF_SHIFT;
 
-    let zf = if result & (!0u64 >> (63 - msb_shift)) == 0 {
-        1
-    } else {
-        0
-    } << ZF_SHIFT;
+    let zf = u64::from(result & (!0u64 >> (63 - msb_shift)) == 0) << ZF_SHIFT;
 
     let sf = ((result >> msb_shift) & 0x1) << SF_SHIFT;
 

hypervisor/src/kvm/aarch64/gic/redist_regs.rs

@@ -200,13 +200,7 @@ pub fn construct_gicr_typers(vcpu_states: &[CpuState]) -> Vec<u64> {
     let mut gicr_typers: Vec<u64> = Vec::new();
     for (index, state) in vcpu_states.iter().enumerate() {
         let state: VcpuKvmState = state.clone().into();
-        let last = {
-            if index == vcpu_states.len() - 1 {
-                1
-            } else {
-                0
-            }
-        };
+        let last = (index == vcpu_states.len() - 1) as u64;
         // state.sys_regs is a big collection of system registers, including MIPDR_EL1
         let mpidr: Vec<Register> = state
             .sys_regs

hypervisor/src/kvm/mod.rs

@@ -822,7 +822,7 @@ impl vm::Vm for KvmVm {
         tdx_command(
             &self.fd.as_raw_fd(),
             TdxCommand::InitMemRegion,
-            if measure { 1 } else { 0 },
+            u32::from(measure),
             &data as *const _ as u64,
         )
         .map_err(vm::HypervisorVmError::InitMemRegionTdx)

qcow/src/qcow.rs

@@ -1582,12 +1582,12 @@ fn offset_is_cluster_boundary(offset: u64, cluster_bits: u32) -> Result<()> {
 
 // Ceiling of the division of `dividend`/`divisor`.
 fn div_round_up_u64(dividend: u64, divisor: u64) -> u64 {
-    dividend / divisor + if dividend % divisor != 0 { 1 } else { 0 }
+    dividend / divisor + u64::from(dividend % divisor != 0)
 }
 
 // Ceiling of the division of `dividend`/`divisor`.
 fn div_round_up_u32(dividend: u32, divisor: u32) -> u32 {
-    dividend / divisor + if dividend % divisor != 0 { 1 } else { 0 }
+    dividend / divisor + u32::from(dividend % divisor != 0)
 }
 
 fn convert_copy<R, W>(reader: &mut R, writer: &mut W, offset: u64, size: u64) -> Result<()>

virtio-devices/src/transport/pci_common_config.rs

@@ -166,13 +166,7 @@ impl VirtioPciCommonConfig {
             0x16 => self.queue_select,
             0x18 => self.with_queue(queues, |q| q.size()).unwrap_or(0),
             0x1a => self.msix_queues.lock().unwrap()[self.queue_select as usize],
-            0x1c => {
-                if self.with_queue(queues, |q| q.ready()).unwrap_or(false) {
-                    1
-                } else {
-                    0
-                }
-            }
+            0x1c => u16::from(self.with_queue(queues, |q| q.ready()).unwrap_or(false)),
             0x1e => self.queue_select, // notify_off
             _ => {
                 warn!("invalid virtio register word read: 0x{:x}", offset);