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hypervisor: x86: handle more registers in emulator
List all GPRs documented in Intel's SDM. Signed-off-by: Wei Liu <liuwe@microsoft.com>
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@ -130,18 +130,18 @@ impl CpuStateManager for EmulatorCpuState {
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Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
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Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
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self.regs.rdx
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self.regs.rdx
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}
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}
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Register::RSP | Register::ESP => self.regs.rsp,
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Register::RSP | Register::ESP | Register::SP => self.regs.rsp,
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Register::RBP | Register::EBP => self.regs.rbp,
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Register::RBP | Register::EBP | Register::BP => self.regs.rbp,
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Register::RSI | Register::ESI => self.regs.rsi,
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Register::RSI | Register::ESI | Register::SI | Register::SIL => self.regs.rsi,
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Register::RDI | Register::EDI | Register::DI | Register::DIL => self.regs.rdi,
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Register::RDI | Register::EDI | Register::DI | Register::DIL => self.regs.rdi,
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Register::R8 | Register::R8D => self.regs.r8,
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Register::R8 | Register::R8D | Register::R8W | Register::R8L => self.regs.r8,
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Register::R9 | Register::R9D => self.regs.r9,
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Register::R9 | Register::R9D | Register::R9W | Register::R9L => self.regs.r9,
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Register::R10 | Register::R10D => self.regs.r10,
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Register::R10 | Register::R10D | Register::R10W | Register::R10L => self.regs.r10,
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Register::R11 | Register::R11D => self.regs.r11,
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Register::R11 | Register::R11D | Register::R11W | Register::R11L => self.regs.r11,
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Register::R12 | Register::R12D => self.regs.r12,
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Register::R12 | Register::R12D | Register::R12W | Register::R12L => self.regs.r12,
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Register::R13 | Register::R13D => self.regs.r13,
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Register::R13 | Register::R13D | Register::R13W | Register::R13L => self.regs.r13,
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Register::R14 | Register::R14D => self.regs.r14,
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Register::R14 | Register::R14D | Register::R14W | Register::R14L => self.regs.r14,
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Register::R15 | Register::R15D => self.regs.r15,
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Register::R15 | Register::R15D | Register::R15W | Register::R15L => self.regs.r15,
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Register::CR0 => self.sregs.cr0,
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Register::CR0 => self.sregs.cr0,
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Register::CR2 => self.sregs.cr2,
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Register::CR2 => self.sregs.cr2,
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Register::CR3 => self.sregs.cr3,
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Register::CR3 => self.sregs.cr3,
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@ -228,40 +228,40 @@ impl CpuStateManager for EmulatorCpuState {
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Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
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Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
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set_reg!(self.regs.rdx, mask, reg_value);
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set_reg!(self.regs.rdx, mask, reg_value);
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}
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}
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Register::RSP | Register::ESP => {
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Register::RSP | Register::ESP | Register::SP => {
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set_reg!(self.regs.rsp, mask, reg_value)
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set_reg!(self.regs.rsp, mask, reg_value)
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}
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}
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Register::RBP | Register::EBP => {
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Register::RBP | Register::EBP | Register::BP => {
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set_reg!(self.regs.rbp, mask, reg_value)
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set_reg!(self.regs.rbp, mask, reg_value)
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}
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}
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Register::RSI | Register::ESI => {
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Register::RSI | Register::ESI | Register::SI | Register::SIL => {
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set_reg!(self.regs.rsi, mask, reg_value)
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set_reg!(self.regs.rsi, mask, reg_value)
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}
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}
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Register::RDI | Register::EDI | Register::DI | Register::DIL => {
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Register::RDI | Register::EDI | Register::DI | Register::DIL => {
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set_reg!(self.regs.rdi, mask, reg_value)
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set_reg!(self.regs.rdi, mask, reg_value)
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}
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}
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Register::R8 | Register::R8D => {
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Register::R8 | Register::R8D | Register::R8W | Register::R8L => {
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set_reg!(self.regs.r8, mask, reg_value)
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set_reg!(self.regs.r8, mask, reg_value)
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}
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}
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Register::R9 | Register::R9D => {
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Register::R9 | Register::R9D | Register::R9W | Register::R9L => {
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set_reg!(self.regs.r9, mask, reg_value)
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set_reg!(self.regs.r9, mask, reg_value)
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}
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}
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Register::R10 | Register::R10D => {
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Register::R10 | Register::R10D | Register::R10W | Register::R10L => {
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set_reg!(self.regs.r10, mask, reg_value)
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set_reg!(self.regs.r10, mask, reg_value)
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}
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}
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Register::R11 | Register::R11D => {
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Register::R11 | Register::R11D | Register::R11W | Register::R11L => {
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set_reg!(self.regs.r11, mask, reg_value)
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set_reg!(self.regs.r11, mask, reg_value)
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}
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}
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Register::R12 | Register::R12D => {
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Register::R12 | Register::R12D | Register::R12W | Register::R12L => {
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set_reg!(self.regs.r12, mask, reg_value)
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set_reg!(self.regs.r12, mask, reg_value)
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}
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}
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Register::R13 | Register::R13D => {
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Register::R13 | Register::R13D | Register::R13W | Register::R13L => {
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set_reg!(self.regs.r13, mask, reg_value)
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set_reg!(self.regs.r13, mask, reg_value)
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}
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}
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Register::R14 | Register::R14D => {
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Register::R14 | Register::R14D | Register::R14W | Register::R14L => {
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set_reg!(self.regs.r14, mask, reg_value)
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set_reg!(self.regs.r14, mask, reg_value)
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}
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}
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Register::R15 | Register::R15D => {
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Register::R15 | Register::R15D | Register::R15W | Register::R15L => {
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set_reg!(self.regs.r15, mask, reg_value)
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set_reg!(self.regs.r15, mask, reg_value)
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}
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}
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Register::CR0 => set_reg!(self.sregs.cr0, mask, reg_value),
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Register::CR0 => set_reg!(self.sregs.cr0, mask, reg_value),
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