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https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-10-01 02:55:45 +00:00
aarch64: Move setup_regs
to hypervisor
`setup_regs` of AArch64 calls KVM sepecific code. Now move it to `hypervisor` crate. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
This commit is contained in:
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@ -6,8 +6,6 @@
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pub mod fdt;
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/// Layout for this aarch64 system.
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pub mod layout;
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/// Logic for configuring aarch64 registers.
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pub mod regs;
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/// Module for loading UEFI binary.
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pub mod uefi;
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@ -37,7 +35,7 @@ pub enum Error {
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InitramfsAddress,
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/// Error configuring the general purpose registers
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RegsConfiguration(regs::Error),
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RegsConfiguration(hypervisor::HypervisorCpuError),
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/// Error configuring the MPIDR register
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VcpuRegMpidr(hypervisor::HypervisorCpuError),
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@ -67,8 +65,12 @@ pub fn configure_vcpu(
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kernel_entry_point: Option<EntryPoint>,
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) -> super::Result<u64> {
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if let Some(kernel_entry_point) = kernel_entry_point {
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regs::setup_regs(vcpu, id, kernel_entry_point.entry_addr.raw_value())
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.map_err(Error::RegsConfiguration)?;
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vcpu.setup_regs(
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id,
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kernel_entry_point.entry_addr.raw_value(),
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super::layout::FDT_START.raw_value(),
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)
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.map_err(Error::RegsConfiguration)?;
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}
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let mpidr = vcpu.read_mpidr().map_err(Error::VcpuRegMpidr)?;
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@ -1,75 +0,0 @@
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// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the THIRD-PARTY file.
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use hypervisor::kvm::kvm_bindings::{
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kvm_regs, user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
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};
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use hypervisor::{arm64_core_reg_id, offset__of};
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use std::sync::Arc;
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use std::{mem, result};
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use vm_memory::Address;
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/// Errors thrown while setting aarch64 registers.
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#[derive(Debug)]
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pub enum Error {
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/// Failed to set core register (PC, PSTATE or general purpose ones).
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SetCoreRegister(hypervisor::HypervisorCpuError),
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/// Failed to get a system register.
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GetSysRegister(hypervisor::HypervisorCpuError),
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}
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type Result<T> = result::Result<T, Error>;
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#[allow(non_upper_case_globals)]
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// PSR (Processor State Register) bits.
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// Taken from arch/arm64/include/uapi/asm/ptrace.h.
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const PSR_MODE_EL1h: u64 = 0x0000_0005;
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const PSR_F_BIT: u64 = 0x0000_0040;
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const PSR_I_BIT: u64 = 0x0000_0080;
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const PSR_A_BIT: u64 = 0x0000_0100;
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const PSR_D_BIT: u64 = 0x0000_0200;
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// Taken from arch/arm64/kvm/inject_fault.c.
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const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
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/// Configure core registers for a given CPU.
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///
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/// # Arguments
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///
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/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
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/// * `cpu_id` - Index of current vcpu.
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/// * `boot_ip` - Starting instruction pointer.
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/// * `mem` - Reserved DRAM for current VM.
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pub fn setup_regs(vcpu: &Arc<dyn hypervisor::Vcpu>, cpu_id: u8, boot_ip: u64) -> Result<()> {
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let kreg_off = offset__of!(kvm_regs, regs);
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// Get the register index of the PSTATE (Processor State) register.
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let pstate = offset__of!(user_pt_regs, pstate) + kreg_off;
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vcpu.set_reg(
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arm64_core_reg_id!(KVM_REG_SIZE_U64, pstate),
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PSTATE_FAULT_BITS_64,
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)
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.map_err(Error::SetCoreRegister)?;
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// Other vCPUs are powered off initially awaiting PSCI wakeup.
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if cpu_id == 0 {
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// Setting the PC (Processor Counter) to the current program address (kernel address).
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let pc = offset__of!(user_pt_regs, pc) + kreg_off;
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vcpu.set_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, pc), boot_ip as u64)
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.map_err(Error::SetCoreRegister)?;
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// Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
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// "The device tree blob (dtb) must be placed on an 8-byte boundary and must
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// not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arm64/booting.txt.
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// We are choosing to place it the end of DRAM. See `get_fdt_addr`.
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let regs0 = offset__of!(user_pt_regs, regs) + kreg_off;
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vcpu.set_reg(
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arm64_core_reg_id!(KVM_REG_SIZE_U64, regs0),
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super::layout::FDT_START.raw_value(),
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)
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.map_err(Error::SetCoreRegister)?;
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}
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Ok(())
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}
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@ -453,6 +453,11 @@ pub trait Vcpu: Send + Sync {
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn read_mpidr(&self) -> Result<u64>;
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///
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/// Configure core registers for a given CPU.
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///
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn setup_regs(&self, cpu_id: u8, boot_ip: u64, fdt_start: u64) -> Result<()>;
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///
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/// Retrieve the vCPU state.
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/// This function is necessary to snapshot the VM
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///
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@ -1566,6 +1566,51 @@ impl cpu::Vcpu for KvmVcpu {
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.get_one_reg(MPIDR_EL1)
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.map_err(|e| cpu::HypervisorCpuError::GetSysRegister(e.into()))
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}
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///
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/// Configure core registers for a given CPU.
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///
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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fn setup_regs(&self, cpu_id: u8, boot_ip: u64, fdt_start: u64) -> cpu::Result<()> {
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#[allow(non_upper_case_globals)]
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// PSR (Processor State Register) bits.
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// Taken from arch/arm64/include/uapi/asm/ptrace.h.
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const PSR_MODE_EL1h: u64 = 0x0000_0005;
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const PSR_F_BIT: u64 = 0x0000_0040;
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const PSR_I_BIT: u64 = 0x0000_0080;
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const PSR_A_BIT: u64 = 0x0000_0100;
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const PSR_D_BIT: u64 = 0x0000_0200;
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// Taken from arch/arm64/kvm/inject_fault.c.
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const PSTATE_FAULT_BITS_64: u64 =
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PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
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let kreg_off = offset__of!(kvm_regs, regs);
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// Get the register index of the PSTATE (Processor State) register.
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let pstate = offset__of!(user_pt_regs, pstate) + kreg_off;
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self.set_reg(
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arm64_core_reg_id!(KVM_REG_SIZE_U64, pstate),
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PSTATE_FAULT_BITS_64,
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)
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.map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
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// Other vCPUs are powered off initially awaiting PSCI wakeup.
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if cpu_id == 0 {
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// Setting the PC (Processor Counter) to the current program address (kernel address).
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let pc = offset__of!(user_pt_regs, pc) + kreg_off;
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self.set_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, pc), boot_ip as u64)
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.map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
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// Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
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// "The device tree blob (dtb) must be placed on an 8-byte boundary and must
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// not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arm64/booting.txt.
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// We are choosing to place it the end of DRAM. See `get_fdt_addr`.
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let regs0 = offset__of!(user_pt_regs, regs) + kreg_off;
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self.set_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, regs0), fdt_start)
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.map_err(|e| cpu::HypervisorCpuError::SetCoreRegister(e.into()))?;
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}
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Ok(())
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}
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#[cfg(target_arch = "x86_64")]
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///
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/// Get the current CPU state
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@ -2436,7 +2436,7 @@ mod tests {
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#[cfg(target_arch = "aarch64")]
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#[cfg(test)]
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mod tests {
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use arch::aarch64::regs::*;
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use arch::layout;
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use hypervisor::kvm::aarch64::{is_system_register, MPIDR_EL1};
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use hypervisor::kvm::kvm_bindings::{
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kvm_one_reg, kvm_regs, kvm_vcpu_init, user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM64_SYSREG,
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@ -2451,7 +2451,7 @@ mod tests {
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let vm = hv.create_vm().unwrap();
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let vcpu = vm.create_vcpu(0, None).unwrap();
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let res = setup_regs(&vcpu, 0, 0x0);
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let res = vcpu.setup_regs(0, 0x0, layout::FDT_START.0);
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// Must fail when vcpu is not initialized yet.
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assert!(res.is_err());
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@ -2459,7 +2459,7 @@ mod tests {
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vm.get_preferred_target(&mut kvi).unwrap();
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vcpu.vcpu_init(&kvi).unwrap();
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assert!(setup_regs(&vcpu, 0, 0x0).is_ok());
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assert!(vcpu.setup_regs(0, 0x0, layout::FDT_START.0).is_ok());
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}
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#[test]
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