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pci: Support DWORD/4-byte writes to the MSI-X control register

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The PCI spec does not specify that the access has to be of a specific
size.

Fixes: #3714

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
(cherry picked from commit 9c6e7c4a4b)
Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford 2022-02-17 10:07:49 +00:00
parent 366223c9f4
commit bbda07c388
1 changed files with 5 additions and 0 deletions
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5
pci/src/configuration.rs
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@ -740,6 +740,11 @@ impl PciConfiguration {
.lock()
.unwrap()
.set_msg_ctl(LittleEndian::read_u16(data));
} else if msix_cap_reg_idx == reg_idx && offset == 0 && data.len() == 4 {
msix_config
.lock()
.unwrap()
.set_msg_ctl((LittleEndian::read_u32(data) >> 16) as u16);
}
}
}